| Message ID | 1513175142-3702-4-git-send-email-absahu@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
On 12/13, Abhishek Sahu wrote: > GPLL0 uses 4 bits post divider which should be specified > in clock driver structure. > > Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> > --- Applied to clk-next
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index ed2d00f..99906f6 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -84,6 +84,7 @@ enum { static struct clk_alpha_pll_postdiv gpll0 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", .parent_names = (const char *[]){
GPLL0 uses 4 bits post divider which should be specified in clock driver structure. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+)