[v1,12/21] RISC-V HART Array

Commit Message

Antony Pavlov Jan. 5, 2018, 9:41 p.m. UTC

On Wed,  3 Jan 2018 13:44:16 +1300
Michael Clark <[e-mail]> wrote:

> Holds the state of a heterogenous array of RISC-V hardware threads.

...

> --- /dev/null
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -0,0 +1,45 @@
> +/*
> + * QEMU RISC-V Hart Array interface
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + *
> + * Holds the state of a heterogenous array of RISC-V harts
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_RISCV_HART_H
> +#define HW_RISCV_HART_H
> +
> +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
> +
> +#define RISCV_HART_ARRAY(obj) \
> +    OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY)
> +
> +typedef struct RISCVHartArrayState {
> +    /*< private >*/
> +    SysBusDevice parent_obj;
> +
> +    /*< public >*/
> +    uint32_t num_harts;
> +    char *cpu_model;
> +    RISCVCPU *harts;
> +} RISCVHartArrayState;
> +
> +#endif
> -- 
> 2.7.0

Hmm, you use SysBusDevice, uint32_t and RISCVCPU types but there is no header files
inclusion to define these types.

I propose this fixup:



Some files in include/hw/riscv/ are affected by this problem (e.g. sifive_uart.h).

Comments

Eric Blake Jan. 5, 2018, 9:44 p.m. UTC | #1

On 01/05/2018 03:41 PM, Antony Pavlov wrote:
> On Wed,  3 Jan 2018 13:44:16 +1300
> Michael Clark <[e-mail]> wrote:
> 
>> Holds the state of a heterogenous array of RISC-V hardware threads.
> 

> 
> Hmm, you use SysBusDevice, uint32_t and RISCVCPU types but there is no header files
> inclusion to define these types.
> 
> I propose this fixup:
> 
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -27,6 +27,10 @@
>  #ifndef HW_RISCV_HART_H
>  #define HW_RISCV_HART_H
>  
> +#include "qemu/osdep.h"

NACK to this part.  Our policy is that all .c files should include
osdep.h before anything else, and therefore, all .h files can assume
that osdep.h has already been included.  Extending that logic, uint32_t
is always available for use in any .h, without having to add any includes.

> +#include "hw/sysbus.h"
> +#include "target/riscv/cpu.h"

But including these headers for SysBusDevice and RISCVCPU makes sense.

Patch

--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -27,6 +27,10 @@ 
 #ifndef HW_RISCV_HART_H
 #define HW_RISCV_HART_H
 
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "target/riscv/cpu.h"
+
 #define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
 
 #define RISCV_HART_ARRAY(obj) \