| Message ID | 20180109232835.11478-3-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 01/09/2018 03:28 PM, Paulo Zanoni wrote: > From: Michel Thierry <michel.thierry@intel.com> > > v2: rebased to intel_lr_indirect_ctx_offset > > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 5 +++++ > 1 file changed, 5 insertions(+) We can add the BSpec tag to the commit message: Bspec: 11740 with that: Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 3c6f587fa903..dab988f20833 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -204,6 +204,7 @@ > #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 > #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 > #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 > +#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A > > /* Typical size of the average request (2 pipecontrols and a MI_BB) */ > #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ > @@ -2148,6 +2149,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) > default: > MISSING_CASE(INTEL_GEN(engine->i915)); > /* fall through */ > + case 11: > + indirect_ctx_offset = > + GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; > + break; > case 10: > indirect_ctx_offset = > GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3c6f587fa903..dab988f20833 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -204,6 +204,7 @@ #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 +#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A /* Typical size of the average request (2 pipecontrols and a MI_BB) */ #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ @@ -2148,6 +2149,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) default: MISSING_CASE(INTEL_GEN(engine->i915)); /* fall through */ + case 11: + indirect_ctx_offset = + GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; case 10: indirect_ctx_offset = GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;