| Message ID | 1517580222-23301-2-git-send-email-gabriel.fernandez@st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 02, 2018 at 03:03:29PM +0100, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > The RCC block is responsible of the management of the clock and reset > generation for the complete circuit. > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > --- > .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt > new file mode 100644 > index 0000000..28017a1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt > @@ -0,0 +1,85 @@ > +STMicroelectronics STM32 Peripheral Reset Clock Controller > +========================================================== > + > +The RCC IP is both a reset and a clock controller. > + > +Please also refer to reset.txt for common reset controller binding usage. > + > +Please also refer to clock-bindings.txt for common clock controller > +binding usage. > + > + > +Required properties: > +- compatible: "simple-mfd", "syscon" > +- reg: should be register base and length as documented in the datasheet > + > +- Sub-nodes: > + - compatible: "st,stm32mp1-rcc-clk" > + - #clock-cells: 1, device nodes should specify the clock in their > + "clocks" property, containing a phandle to the clock device node, > + an index specifying the clock to use. > + > + - compatible: "st,stm32mp1-rcc-rst" > + - #reset-cells: Shall be 1 > + > +Example: > + rcc: rcc@50000000 { > + compatible = "syscon", "simple-mfd"; > + reg = <0x50000000 0x1000>; > + > + rcc_clk: rcc-clk@50000000 { > + #clock-cells = <1>; > + compatible = "st,stm32mp1-rcc-clk"; > + }; > + > + rcc_rst: rcc-reset@50000000 { You should not have the same unit-address twice. IMO, this should just be: rcc: rcc@50000000 { compatible = "st-stm32mp1-rcc"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; There's no reason a node can't provide more than 1 function. > + #reset-cells = <1>; > + compatible = "st,stm32mp1-rcc-rst"; > + }; > + }; > + > +Specifying clocks > +================= > + > +All available clocks are defined as preprocessor macros in > +dt-bindings/clock/stm32mp1-clks.h header and can be used in device > +tree sources. > + > +Example: > + > + /* Accessing DMA1 clock */ > + ... { > + clocks = <&rcc_clk DMA1> > + }; > + > + /* Accessing SPI6 kernel clock */ > + ... { > + clocks = <&rcc_clk SPI6_K> > + }; Other than the path to header, the clock binding explains all this. No need to duplicate here. > + > +Specifying softreset control of devices > +======================================= > + > +Device nodes should specify the reset channel required in their "resets" > +property, containing a phandle to the reset device node and an index specifying > +which channel to use. > +The index is the bit number within the RCC registers bank, starting from RCC > +base address. > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register. > + > +For example on STM32MP1, for LTDC reset: > + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset > + = 0x180 / 4 * 32 + 0 = 3072 > + > +The list of valid indices for STM32MP1 is available in: > +include/dt-bindings/reset-controller/stm32mp1-resets.h > + > +This file implements defines like: > +#define LTDC_R 3072 > + > +example: > + > + ltdc { > + resets = <&rcc_rst LTDC_R>; > + }; > -- > 1.9.1 >
Hi Rob, Thanks for reviewing. On 02/05/2018 07:09 AM, Rob Herring wrote: > On Fri, Feb 02, 2018 at 03:03:29PM +0100, gabriel.fernandez@st.com wrote: >> From: Gabriel Fernandez <gabriel.fernandez@st.com> >> >> The RCC block is responsible of the management of the clock and reset >> generation for the complete circuit. >> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> >> --- >> .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> >> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> new file mode 100644 >> index 0000000..28017a1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> @@ -0,0 +1,85 @@ >> +STMicroelectronics STM32 Peripheral Reset Clock Controller >> +========================================================== >> + >> +The RCC IP is both a reset and a clock controller. >> + >> +Please also refer to reset.txt for common reset controller binding usage. >> + >> +Please also refer to clock-bindings.txt for common clock controller >> +binding usage. >> + >> + >> +Required properties: >> +- compatible: "simple-mfd", "syscon" > >> +- reg: should be register base and length as documented in the datasheet >> + >> +- Sub-nodes: >> + - compatible: "st,stm32mp1-rcc-clk" >> + - #clock-cells: 1, device nodes should specify the clock in their >> + "clocks" property, containing a phandle to the clock device node, >> + an index specifying the clock to use. >> + >> + - compatible: "st,stm32mp1-rcc-rst" >> + - #reset-cells: Shall be 1 >> + >> +Example: >> + rcc: rcc@50000000 { >> + compatible = "syscon", "simple-mfd"; >> + reg = <0x50000000 0x1000>; >> + >> + rcc_clk: rcc-clk@50000000 { >> + #clock-cells = <1>; >> + compatible = "st,stm32mp1-rcc-clk"; >> + }; >> + >> + rcc_rst: rcc-reset@50000000 { > You should not have the same unit-address twice. > > IMO, this should just be: > > rcc: rcc@50000000 { > compatible = "st-stm32mp1-rcc"; > reg = <0x50000000 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > > There's no reason a node can't provide more than 1 function. RCC is an dedicated IP for clocks and resets, but also for power management (patches will be sent later) Then i need to probe 3 drivers with same IP. It's also a way to avoid use of 'CLK_OF_DECLARE_DRIVER' and i need it to probe the 3th driver. BR Gabriel > > >> + #reset-cells = <1>; >> + compatible = "st,stm32mp1-rcc-rst"; >> + }; >> + }; >> + >> +Specifying clocks >> +================= >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/stm32mp1-clks.h header and can be used in device >> +tree sources. >> + >> +Example: >> + >> + /* Accessing DMA1 clock */ >> + ... { >> + clocks = <&rcc_clk DMA1> >> + }; >> + >> + /* Accessing SPI6 kernel clock */ >> + ... { >> + clocks = <&rcc_clk SPI6_K> >> + }; > Other than the path to header, the clock binding explains all this. No > need to duplicate here. ok >> + >> +Specifying softreset control of devices >> +======================================= >> + >> +Device nodes should specify the reset channel required in their "resets" >> +property, containing a phandle to the reset device node and an index specifying >> +which channel to use. >> +The index is the bit number within the RCC registers bank, starting from RCC >> +base address. >> +It is calculated as: index = register_offset / 4 * 32 + bit_offset. >> +Where bit_offset is the bit offset within the register. >> + >> +For example on STM32MP1, for LTDC reset: >> + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset >> + = 0x180 / 4 * 32 + 0 = 3072 >> + >> +The list of valid indices for STM32MP1 is available in: >> +include/dt-bindings/reset-controller/stm32mp1-resets.h >> + >> +This file implements defines like: >> +#define LTDC_R 3072 >> + >> +example: >> + >> + ltdc { >> + resets = <&rcc_rst LTDC_R>; >> + }; >> -- >> 1.9.1 >>
On 02/05/2018 07:09 AM, Rob Herring wrote: > On Fri, Feb 02, 2018 at 03:03:29PM +0100, gabriel.fernandez@st.com wrote: >> From: Gabriel Fernandez <gabriel.fernandez@st.com> >> >> The RCC block is responsible of the management of the clock and reset >> generation for the complete circuit. >> >> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> >> --- >> .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> >> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> new file mode 100644 >> index 0000000..28017a1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >> @@ -0,0 +1,85 @@ >> +STMicroelectronics STM32 Peripheral Reset Clock Controller >> +========================================================== >> + >> +The RCC IP is both a reset and a clock controller. >> + >> +Please also refer to reset.txt for common reset controller binding usage. >> + >> +Please also refer to clock-bindings.txt for common clock controller >> +binding usage. >> + >> + >> +Required properties: >> +- compatible: "simple-mfd", "syscon" > >> +- reg: should be register base and length as documented in the datasheet >> + >> +- Sub-nodes: >> + - compatible: "st,stm32mp1-rcc-clk" >> + - #clock-cells: 1, device nodes should specify the clock in their >> + "clocks" property, containing a phandle to the clock device node, >> + an index specifying the clock to use. >> + >> + - compatible: "st,stm32mp1-rcc-rst" >> + - #reset-cells: Shall be 1 >> + >> +Example: >> + rcc: rcc@50000000 { >> + compatible = "syscon", "simple-mfd"; >> + reg = <0x50000000 0x1000>; >> + >> + rcc_clk: rcc-clk@50000000 { >> + #clock-cells = <1>; >> + compatible = "st,stm32mp1-rcc-clk"; >> + }; >> + >> + rcc_rst: rcc-reset@50000000 { > You should not have the same unit-address twice. i can change if you want into: rcc: rcc@50000000 { compatible = "syscon", "simple-mfd"; reg = <0x50000000 0x1000>; rcc_clk: rcc-clk { #clock-cells = <1>; compatible = "st,stm32mp1-rcc-clk"; }; rcc_rst: rcc-reset { #reset-cells = <1>; compatible = "st,stm32mp1-rcc-rst"; }; BR Gabriel > IMO, this should just be: > > rcc: rcc@50000000 { > compatible = "st-stm32mp1-rcc"; > reg = <0x50000000 0x1000>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > > There's no reason a node can't provide more than 1 function. > > >> + #reset-cells = <1>; >> + compatible = "st,stm32mp1-rcc-rst"; >> + }; >> + }; >> + >> +Specifying clocks >> +================= >> + >> +All available clocks are defined as preprocessor macros in >> +dt-bindings/clock/stm32mp1-clks.h header and can be used in device >> +tree sources. >> + >> +Example: >> + >> + /* Accessing DMA1 clock */ >> + ... { >> + clocks = <&rcc_clk DMA1> >> + }; >> + >> + /* Accessing SPI6 kernel clock */ >> + ... { >> + clocks = <&rcc_clk SPI6_K> >> + }; > Other than the path to header, the clock binding explains all this. No > need to duplicate here. > >> + >> +Specifying softreset control of devices >> +======================================= >> + >> +Device nodes should specify the reset channel required in their "resets" >> +property, containing a phandle to the reset device node and an index specifying >> +which channel to use. >> +The index is the bit number within the RCC registers bank, starting from RCC >> +base address. >> +It is calculated as: index = register_offset / 4 * 32 + bit_offset. >> +Where bit_offset is the bit offset within the register. >> + >> +For example on STM32MP1, for LTDC reset: >> + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset >> + = 0x180 / 4 * 32 + 0 = 3072 >> + >> +The list of valid indices for STM32MP1 is available in: >> +include/dt-bindings/reset-controller/stm32mp1-resets.h >> + >> +This file implements defines like: >> +#define LTDC_R 3072 >> + >> +example: >> + >> + ltdc { >> + resets = <&rcc_rst LTDC_R>; >> + }; >> -- >> 1.9.1 >>
On Mon, Feb 5, 2018 at 1:01 AM, Gabriel FERNANDEZ <gabriel.fernandez@st.com> wrote: > Hi Rob, > > Thanks for reviewing. > > > On 02/05/2018 07:09 AM, Rob Herring wrote: >> On Fri, Feb 02, 2018 at 03:03:29PM +0100, gabriel.fernandez@st.com wrote: >>> From: Gabriel Fernandez <gabriel.fernandez@st.com> >>> >>> The RCC block is responsible of the management of the clock and reset >>> generation for the complete circuit. >>> >>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> >>> --- >>> .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ >>> 1 file changed, 85 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>> >>> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>> new file mode 100644 >>> index 0000000..28017a1 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>> @@ -0,0 +1,85 @@ >>> +STMicroelectronics STM32 Peripheral Reset Clock Controller >>> +========================================================== >>> + >>> +The RCC IP is both a reset and a clock controller. >>> + >>> +Please also refer to reset.txt for common reset controller binding usage. >>> + >>> +Please also refer to clock-bindings.txt for common clock controller >>> +binding usage. >>> + >>> + >>> +Required properties: >>> +- compatible: "simple-mfd", "syscon" >> >>> +- reg: should be register base and length as documented in the datasheet >>> + >>> +- Sub-nodes: >>> + - compatible: "st,stm32mp1-rcc-clk" >>> + - #clock-cells: 1, device nodes should specify the clock in their >>> + "clocks" property, containing a phandle to the clock device node, >>> + an index specifying the clock to use. >>> + >>> + - compatible: "st,stm32mp1-rcc-rst" >>> + - #reset-cells: Shall be 1 >>> + >>> +Example: >>> + rcc: rcc@50000000 { >>> + compatible = "syscon", "simple-mfd"; >>> + reg = <0x50000000 0x1000>; >>> + >>> + rcc_clk: rcc-clk@50000000 { >>> + #clock-cells = <1>; >>> + compatible = "st,stm32mp1-rcc-clk"; >>> + }; >>> + >>> + rcc_rst: rcc-reset@50000000 { >> You should not have the same unit-address twice. >> >> IMO, this should just be: >> >> rcc: rcc@50000000 { >> compatible = "st-stm32mp1-rcc"; >> reg = <0x50000000 0x1000>; >> #clock-cells = <1>; >> #reset-cells = <1>; >> }; >> >> There's no reason a node can't provide more than 1 function. > RCC is an dedicated IP for clocks and resets, but also for power > management (patches will be sent later) If there's additional functions, they should be part of the binding now, not later. bindings should not unnecessarily evolve. > Then i need to probe 3 drivers with same IP. Drivers and DT nodes don't have to be 1-1. A parent driver can create additional child devices. Also, looking at your existing bindings for RCC IP, it is done as I suggested. > It's also a way to avoid use of 'CLK_OF_DECLARE_DRIVER' and i need it to > probe the 3th driver. Sounds like a Linux problem, not a DT issue. Rob
On 02/07/2018 07:03 PM, Rob Herring wrote: > On Mon, Feb 5, 2018 at 1:01 AM, Gabriel FERNANDEZ > <gabriel.fernandez@st.com> wrote: >> Hi Rob, >> >> Thanks for reviewing. >> >> >> On 02/05/2018 07:09 AM, Rob Herring wrote: >>> On Fri, Feb 02, 2018 at 03:03:29PM +0100,gabriel.fernandez@st.com wrote: >>>> From: Gabriel Fernandez<gabriel.fernandez@st.com> >>>> >>>> The RCC block is responsible of the management of the clock and reset >>>> generation for the complete circuit. >>>> >>>> Signed-off-by: Gabriel Fernandez<gabriel.fernandez@st.com> >>>> --- >>>> .../devicetree/bindings/mfd/st,stm32-rcc.txt | 85 ++++++++++++++++++++++ >>>> 1 file changed, 85 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>>> new file mode 100644 >>>> index 0000000..28017a1 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt >>>> @@ -0,0 +1,85 @@ >>>> +STMicroelectronics STM32 Peripheral Reset Clock Controller >>>> +========================================================== >>>> + >>>> +The RCC IP is both a reset and a clock controller. >>>> + >>>> +Please also refer to reset.txt for common reset controller binding usage. >>>> + >>>> +Please also refer to clock-bindings.txt for common clock controller >>>> +binding usage. >>>> + >>>> + >>>> +Required properties: >>>> +- compatible: "simple-mfd", "syscon" >>>> +- reg: should be register base and length as documented in the datasheet >>>> + >>>> +- Sub-nodes: >>>> + - compatible: "st,stm32mp1-rcc-clk" >>>> + - #clock-cells: 1, device nodes should specify the clock in their >>>> + "clocks" property, containing a phandle to the clock device node, >>>> + an index specifying the clock to use. >>>> + >>>> + - compatible: "st,stm32mp1-rcc-rst" >>>> + - #reset-cells: Shall be 1 >>>> + >>>> +Example: >>>> + rcc: rcc@50000000 { >>>> + compatible = "syscon", "simple-mfd"; >>>> + reg = <0x50000000 0x1000>; >>>> + >>>> + rcc_clk: rcc-clk@50000000 { >>>> + #clock-cells = <1>; >>>> + compatible = "st,stm32mp1-rcc-clk"; >>>> + }; >>>> + >>>> + rcc_rst: rcc-reset@50000000 { >>> You should not have the same unit-address twice. >>> >>> IMO, this should just be: >>> >>> rcc: rcc@50000000 { >>> compatible = "st-stm32mp1-rcc"; >>> reg = <0x50000000 0x1000>; >>> #clock-cells = <1>; >>> #reset-cells = <1>; >>> }; >>> >>> There's no reason a node can't provide more than 1 function. >> RCC is an dedicated IP for clocks and resets, but also for power >> management (patches will be sent later) > If there's additional functions, they should be part of the binding > now, not later. bindings should not unnecessarily evolve. Yes you're right i will do it. >> Then i need to probe 3 drivers with same IP. > Drivers and DT nodes don't have to be 1-1. A parent driver can create > additional child devices. > > Also, looking at your existing bindings for RCC IP, it is done as I suggested. > >> It's also a way to avoid use of 'CLK_OF_DECLARE_DRIVER' and i need it to >> probe the 3th driver. > Sounds like a Linux problem, not a DT issue. > > Rob RCC is an IP block wich exposed multiple functionalities (clock, reset, power management), mfd should be the best solution to populate each functionality in natural way, and to access to registers ? Gabriel
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt new file mode 100644 index 0000000..28017a1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/st,stm32-rcc.txt @@ -0,0 +1,85 @@ +STMicroelectronics STM32 Peripheral Reset Clock Controller +========================================================== + +The RCC IP is both a reset and a clock controller. + +Please also refer to reset.txt for common reset controller binding usage. + +Please also refer to clock-bindings.txt for common clock controller +binding usage. + + +Required properties: +- compatible: "simple-mfd", "syscon" +- reg: should be register base and length as documented in the datasheet + +- Sub-nodes: + - compatible: "st,stm32mp1-rcc-clk" + - #clock-cells: 1, device nodes should specify the clock in their + "clocks" property, containing a phandle to the clock device node, + an index specifying the clock to use. + + - compatible: "st,stm32mp1-rcc-rst" + - #reset-cells: Shall be 1 + +Example: + rcc: rcc@50000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x50000000 0x1000>; + + rcc_clk: rcc-clk@50000000 { + #clock-cells = <1>; + compatible = "st,stm32mp1-rcc-clk"; + }; + + rcc_rst: rcc-reset@50000000 { + #reset-cells = <1>; + compatible = "st,stm32mp1-rcc-rst"; + }; + }; + +Specifying clocks +================= + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/stm32mp1-clks.h header and can be used in device +tree sources. + +Example: + + /* Accessing DMA1 clock */ + ... { + clocks = <&rcc_clk DMA1> + }; + + /* Accessing SPI6 kernel clock */ + ... { + clocks = <&rcc_clk SPI6_K> + }; + +Specifying softreset control of devices +======================================= + +Device nodes should specify the reset channel required in their "resets" +property, containing a phandle to the reset device node and an index specifying +which channel to use. +The index is the bit number within the RCC registers bank, starting from RCC +base address. +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register. + +For example on STM32MP1, for LTDC reset: + ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset + = 0x180 / 4 * 32 + 0 = 3072 + +The list of valid indices for STM32MP1 is available in: +include/dt-bindings/reset-controller/stm32mp1-resets.h + +This file implements defines like: +#define LTDC_R 3072 + +example: + + ltdc { + resets = <&rcc_rst LTDC_R>; + };