| Message ID | fc5bdf53b92bd7a96e94b714d8d13deebca95c28.1517910489.git.sean.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06-02-18, 17:52, sean.wang@mediatek.com wrote: > cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -26,6 +70,10 @@ > device_type = "cpu"; > compatible = "arm,cortex-a53", "arm,armv8"; > reg = <0x0 0x0>; > + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, > + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; > + clock-names = "cpu", "intermediate"; > + operating-points-v2 = <&cpu_opp_table>; > enable-method = "psci"; > clock-frequency = <1300000000>; > }; > @@ -34,6 +82,7 @@ > device_type = "cpu"; > compatible = "arm,cortex-a53", "arm,armv8"; > reg = <0x0 0x1>; > + operating-points-v2 = <&cpu_opp_table>; > enable-method = "psci"; > clock-frequency = <1300000000>; > }; Sorry for not picking this earlier, but you should probably add the same clock related properties for both cpu nodes here. Things will break if CPU1 is used by the cpufreq core to bring the cpufreq policy online. This can happen if cpufreq driver is a module, CPU0 is hotplugged out and then the cpufreq driver is inserted.
On Wed, 2018-02-07 at 09:03 +0530, Viresh Kumar wrote: > On 06-02-18, 17:52, sean.wang@mediatek.com wrote: > > cpus { > > #address-cells = <2>; > > #size-cells = <0>; > > @@ -26,6 +70,10 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a53", "arm,armv8"; > > reg = <0x0 0x0>; > > + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, > > + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; > > + clock-names = "cpu", "intermediate"; > > + operating-points-v2 = <&cpu_opp_table>; > > enable-method = "psci"; > > clock-frequency = <1300000000>; > > }; > > @@ -34,6 +82,7 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a53", "arm,armv8"; > > reg = <0x0 0x1>; > > + operating-points-v2 = <&cpu_opp_table>; > > enable-method = "psci"; > > clock-frequency = <1300000000>; > > }; > > Sorry for not picking this earlier, but you should probably add the same clock > related properties for both cpu nodes here. Things will break if CPU1 is used by > the cpufreq core to bring the cpufreq policy online. > > This can happen if cpufreq driver is a module, CPU0 is hotplugged out and then > the cpufreq driver is inserted. > mt7622 cpu0 does not support hotplug. do I still need to add same clock related properties for both cpu nodes here?
On 07-02-18, 14:16, Sean Wang wrote: > On Wed, 2018-02-07 at 09:03 +0530, Viresh Kumar wrote: > > On 06-02-18, 17:52, sean.wang@mediatek.com wrote: > > > cpus { > > > #address-cells = <2>; > > > #size-cells = <0>; > > > @@ -26,6 +70,10 @@ > > > device_type = "cpu"; > > > compatible = "arm,cortex-a53", "arm,armv8"; > > > reg = <0x0 0x0>; > > > + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, > > > + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; > > > + clock-names = "cpu", "intermediate"; > > > + operating-points-v2 = <&cpu_opp_table>; > > > enable-method = "psci"; > > > clock-frequency = <1300000000>; > > > }; > > > @@ -34,6 +82,7 @@ > > > device_type = "cpu"; > > > compatible = "arm,cortex-a53", "arm,armv8"; > > > reg = <0x0 0x1>; > > > + operating-points-v2 = <&cpu_opp_table>; > > > enable-method = "psci"; > > > clock-frequency = <1300000000>; > > > }; > > > > Sorry for not picking this earlier, but you should probably add the same clock > > related properties for both cpu nodes here. Things will break if CPU1 is used by > > the cpufreq core to bring the cpufreq policy online. > > > > This can happen if cpufreq driver is a module, CPU0 is hotplugged out and then > > the cpufreq driver is inserted. > > > > mt7622 cpu0 does not support hotplug. do I still need to add same clock > related properties for both cpu nodes here? Normally we should always add these properties to all the CPUs, as that's the real scenario hardware configuration wise. But I am not sure if something else will break if you don't provide clocks in CPU1. @Rob @Mark: What do you suggest ?
On Wed, 2018-02-07 at 11:48 +0530, Viresh Kumar wrote: > On 07-02-18, 14:16, Sean Wang wrote: > > On Wed, 2018-02-07 at 09:03 +0530, Viresh Kumar wrote: > > > On 06-02-18, 17:52, sean.wang@mediatek.com wrote: > > > > cpus { > > > > #address-cells = <2>; > > > > #size-cells = <0>; > > > > @@ -26,6 +70,10 @@ > > > > device_type = "cpu"; > > > > compatible = "arm,cortex-a53", "arm,armv8"; > > > > reg = <0x0 0x0>; > > > > + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, > > > > + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; > > > > + clock-names = "cpu", "intermediate"; > > > > + operating-points-v2 = <&cpu_opp_table>; > > > > enable-method = "psci"; > > > > clock-frequency = <1300000000>; > > > > }; > > > > @@ -34,6 +82,7 @@ > > > > device_type = "cpu"; > > > > compatible = "arm,cortex-a53", "arm,armv8"; > > > > reg = <0x0 0x1>; > > > > + operating-points-v2 = <&cpu_opp_table>; > > > > enable-method = "psci"; > > > > clock-frequency = <1300000000>; > > > > }; > > > > > > Sorry for not picking this earlier, but you should probably add the same clock > > > related properties for both cpu nodes here. Things will break if CPU1 is used by > > > the cpufreq core to bring the cpufreq policy online. > > > > > > This can happen if cpufreq driver is a module, CPU0 is hotplugged out and then > > > the cpufreq driver is inserted. > > > > > > > mt7622 cpu0 does not support hotplug. do I still need to add same clock > > related properties for both cpu nodes here? > > Normally we should always add these properties to all the CPUs, as that's the > real scenario hardware configuration wise. > Agree on, I will add these missing clock properties also into the cpu1 node to reflect the hardware actually should have. That also is devicetree wants us to do to describe the device more closely. > But I am not sure if something else will break if you don't provide clocks in > CPU1. > > @Rob @Mark: What do you suggest ? >
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 4615af6..bbf4d03 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -20,6 +20,18 @@ bootargs = "console=ttyS0,115200n1"; }; + cpus { + cpu@0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + + cpu@1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; + }; + }; + gpio-keys { compatible = "gpio-keys-polled"; poll-interval = <100>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index c387c4c..65eb417 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -18,6 +18,50 @@ #address-cells = <2>; #size-cells = <2>; + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + opp-300000000 { + opp-hz = /bits/ 64 <30000000>; + opp-microvolt = <950000>; + }; + + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000>; + }; + + opp-812500000 { + opp-hz = /bits/ 64 <812500000>; + opp-microvolt = <1100000>; + }; + + opp-1025000000 { + opp-hz = /bits/ 64 <1025000000>; + opp-microvolt = <1150000>; + }; + + opp-1137500000 { + opp-hz = /bits/ 64 <1137500000>; + opp-microvolt = <1200000>; + }; + + opp-1262500000 { + opp-hz = /bits/ 64 <1262500000>; + opp-microvolt = <1250000>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1310000>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -26,6 +70,10 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; + clocks = <&infracfg CLK_INFRA_MUX1_SEL>, + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; clock-frequency = <1300000000>; }; @@ -34,6 +82,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; + operating-points-v2 = <&cpu_opp_table>; enable-method = "psci"; clock-frequency = <1300000000>; };