| Message ID | 1453205888-8985-5-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
On Tue, Jan 19, 2016 at 1:18 PM, Ulrich Hecht <ulrich.hecht+renesas@gmail.com> wrote: > From: Ryo Kodama <ryo.kodama.vz@renesas.com> > > Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> > Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> > [uli: adapted to new MSTP clock scheme] > Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> > --- > .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + > arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 21 ++++++++++ > arch/arm64/boot/dts/renesas/r8a7795.dtsi | 48 ++++++++++++++++++++++ > 3 files changed, 70 insertions(+) This should be split in 3 patches: - One to update the binding docs, - One to add the PWM device nodes to r8a7795.dtsi, - One to enable PWM on Salvator-X. > --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts > +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts > @@ -93,6 +93,15 @@ > }; > > &pfc { > + pwm1_pins: pwm1 { > + renesas,groups = "pwm1_a", "pwm1_b"; > + renesas,function = "pwm1"; Enabling both pwm1_a and pwm1_b? The LTC2644CMS-L8 DAC providing backlight is connected to pwm1_a, depending on the state of switch SW5. > + }; > + pwm2_pins: pwm2 { > + renesas,groups = "pwm2_a", "pwm2_b"; > + renesas,function = "pwm2"; Enabling both pwm2_a and pwm2_b? The BD9571MWV-M PMIC is connected to pwm2_a, depending on the state of switch SW6. > + }; > @@ -174,6 +183,18 @@ > }; > }; > > +&pwm1 { > + pinctrl-0 = <&pwm1_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&pwm2 { > + pinctrl-0 = <&pwm2_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; It would be good to have a comment explaining what these are actually used for. > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > index bb353cd..3c88b04 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -446,6 +446,54 @@ > status = "disabled"; > }; > > + pwm1: pwm@e6e31000 { > + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; > + reg = <0 0xe6e31000 0 0x10>; > + #pwm-cells = <2>; > + clocks = <&cpg CPG_MOD 523>; Missing "power-domains = <&cpg>;", for all nodes. Note that CPG module clock 523 is not yet provided by drivers/clk/shmobile/r8a7795-cpg-mssr.c. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hello! On 1/19/2016 3:18 PM, Ulrich Hecht wrote: > From: Ryo Kodama <ryo.kodama.vz@renesas.com> > > Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> > Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> > [uli: adapted to new MSTP clock scheme] > Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> [...] > diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts > index 265d12f..04661cf 100644 > --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts > +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts > @@ -93,6 +93,15 @@ > }; > > &pfc { > + pwm1_pins: pwm1 { > + renesas,groups = "pwm1_a", "pwm1_b"; Why both PWM1_A and PWM1_B? Aren't you supposed to select one? > + renesas,function = "pwm1"; > + }; > + pwm2_pins: pwm2 { > + renesas,groups = "pwm2_a", "pwm2_b"; Same here... > + renesas,function = "pwm2"; > + }; > + > scif1_pins: scif1 { > renesas,groups = "scif1_data_a", "scif1_ctrl"; > renesas,function = "scif1"; [...] MBR, Sergei
On 2/23/2018 1:09 PM, Sergei Shtylyov wrote: >> From: Ryo Kodama <ryo.kodama.vz@renesas.com> >> >> Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> >> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> >> [uli: adapted to new MSTP clock scheme] >> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Sorry, I didn't realize I was replying to a month-old patch (with the A/B issue already commented on). MBR, Sergei
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt index 0822a08..d6de643 100644 --- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt +++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,pwm-r8a7790": for R-Car H2 - "renesas,pwm-r8a7791": for R-Car M2-W - "renesas,pwm-r8a7794": for R-Car E2 + - "renesas,pwm-r8a7795": for R-Car H3 - reg: base address and length of the registers block for the PWM. - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format. diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 265d12f..04661cf 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -93,6 +93,15 @@ }; &pfc { + pwm1_pins: pwm1 { + renesas,groups = "pwm1_a", "pwm1_b"; + renesas,function = "pwm1"; + }; + pwm2_pins: pwm2 { + renesas,groups = "pwm2_a", "pwm2_b"; + renesas,function = "pwm2"; + }; + scif1_pins: scif1 { renesas,groups = "scif1_data_a", "scif1_ctrl"; renesas,function = "scif1"; @@ -174,6 +183,18 @@ }; }; +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &rcar_sound { pinctrl-0 = <&sound_pins &sound_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index bb353cd..3c88b04 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -446,6 +446,54 @@ status = "disabled"; }; + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a7795", "renesas,scif"; reg = <0 0xe6e60000 0 64>;