diff mbox

[v4,08/10] ARM: sunxi: smp: Move assembly code into a file

Message ID 20180223133742.26044-9-mylene.josserand@bootlin.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mylène Josserand Feb. 23, 2018, 1:37 p.m. UTC 
Move the assembly code for cluster cache enabling
into an assembly file instead of having it directly in C code.

Create a sunxi_boot entry that will perform a cluster cached
enabling and called secondary_startup.

Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
---
 arch/arm/mach-sunxi/Makefile  |  1 +
 arch/arm/mach-sunxi/headsmp.S | 73 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/mc_smp.c  | 76 ++++---------------------------------------
 3 files changed, 80 insertions(+), 70 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

Comments

Maxime Ripard Feb. 23, 2018, 3:09 p.m. UTC | #1 
On Fri, Feb 23, 2018 at 02:37:40PM +0100, Mylène Josserand wrote:
> Move the assembly code for cluster cache enabling
> into an assembly file instead of having it directly in C code.
> 
> Create a sunxi_boot entry that will perform a cluster cached
> enabling and called secondary_startup.
> 
> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> ---
>  arch/arm/mach-sunxi/Makefile  |  1 +
>  arch/arm/mach-sunxi/headsmp.S | 73 +++++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-sunxi/mc_smp.c  | 76 ++++---------------------------------------
>  3 files changed, 80 insertions(+), 70 deletions(-)
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> 
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 7de9cc286d53..d1a072b879ed 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -1,5 +1,6 @@
>  CFLAGS_mc_smp.o	+= -march=armv7-a
>  
>  obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
>  obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
>  obj-$(CONFIG_SMP) += platsmp.o
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> new file mode 100644
> index 000000000000..4f5957a6e188
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -0,0 +1,73 @@
> +/*
> + * SMP support for sunxi based systems with Cortex A7/A15
> + *
> + * Copyright (C) 2018 Bootlin

This is just a copy, and while you can claim that you are one of the
copyrights holder, you are not the sole one and the original author
should be there.

> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.

You want to use SPDX there instead.

> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> +
> +ENTRY(sunxi_mc_smp_cluster_cache_enable)
> +	/*
> +	* Enable cluster-level coherency, in preparation for turning on the MMU.
> +	*
> +	* Also enable regional clock gating and L2 data latency settings for
> +	* Cortex-A15. These settings are from the vendor kernel.
> +	*/

The indentation is not correct there, the * should be aligned

> +	mrc	p15, 0, r1, c0, c0, 0
> +	movw	r2, #(0xff00fff0&0xffff)
> +	movt	r2, #(0xff00fff0>>16)

This used to be defines, we should keep them, and we should have
spaces around the operators as well.

> +	and	r1, r1, r2
> +	movw	r2, #(0x4100c0f0&0xffff)
> +	movt	r2, #(0x4100c0f0>>16)
> +	cmp	r1, r2
> +	bne	not_a15
> +
> +	/* The following is Cortex-A15 specific */
> +
> +	/* ACTLR2: Enable CPU regional clock gates */
> +	mrc p15, 1, r1, c15, c0, 4
> +	orr r1, r1, #(0x1<<31)
> +	mcr p15, 1, r1, c15, c0, 4
> +
> +	/* L2ACTLR */
> +	mrc p15, 1, r1, c15, c0, 0
> +	/* Enable L2, GIC, and Timer regional clock gates */
> +	orr r1, r1, #(0x1<<26)
> +	/* Disable clean/evict from being pushed to external */
> +	orr r1, r1, #(0x1<<3)
> +	mcr p15, 1, r1, c15, c0, 0
> +
> +	/* L2CTRL: L2 data RAM latency */
> +	mrc p15, 1, r1, c9, c0, 2
> +	bic r1, r1, #(0x7<<0)
> +	orr r1, r1, #(0x3<<0)
> +	mcr p15, 1, r1, c9, c0, 2
> +
> +	/* End of Cortex-A15 specific setup */
> +	not_a15:
> +
> +	/* Get value of sunxi_mc_smp_first_comer */
> +	adr	r1, first
> +	ldr	r0, [r1]
> +	ldr	r0, [r1, r0]
> +
> +	/* Skip cci_enable_port_for_self if not first comer */
> +	cmp	r0, #0
> +	bxeq	lr
> +	b	cci_enable_port_for_self
> +
> +	.align 2
> +	first: .word sunxi_mc_smp_first_comer - .
> +ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> +
> +#ifdef CONFIG_SMP

I guess that whole file should be compiled only if we have SMP
enabled.

> +ENTRY(sunxi_boot)
> +	bl	sunxi_mc_smp_cluster_cache_enable
> +	b	secondary_startup
> +ENDPROC(sunxi_boot)
> +#endif
> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> index f2c2cfca28cd..4e807cc11a0f 100644
> --- a/arch/arm/mach-sunxi/mc_smp.c
> +++ b/arch/arm/mach-sunxi/mc_smp.c
> @@ -82,6 +82,9 @@ static void __iomem *prcm_base;
>  static void __iomem *sram_b_smp_base;
>  static bool is_sun9i;
>  
> +extern void sunxi_boot(void);

Why did you change the name of that function? The older one made it
more obvious to tell what is going on.

> +extern void sunxi_cluster_cache_enable(void);

Is that used somewhere?

Thanks!
Maxime
kernel test robot Feb. 26, 2018, 6:22 a.m. UTC | #2 
Hi Mylène,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180223]
[cannot apply to arm-soc/for-next robh/for-next linux-rpi/for-rpi-next v4.16-rc2 v4.16-rc1 v4.15 v4.16-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Myl-ne-Josserand/Sunxi-Add-SMP-support-on-A83T/20180226-035312
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   arch/arm/mach-sunxi/headsmp.S: Assembler messages:
>> arch/arm/mach-sunxi/headsmp.S:22: Error: selected processor does not support `movw r2,#(0xff00fff0&0xffff)' in ARM mode
>> arch/arm/mach-sunxi/headsmp.S:23: Error: selected processor does not support `movt r2,#(0xff00fff0>>16)' in ARM mode
   arch/arm/mach-sunxi/headsmp.S:25: Error: selected processor does not support `movw r2,#(0x4100c0f0&0xffff)' in ARM mode
   arch/arm/mach-sunxi/headsmp.S:26: Error: selected processor does not support `movt r2,#(0x4100c0f0>>16)' in ARM mode

vim +22 arch/arm/mach-sunxi/headsmp.S

    13	
    14	ENTRY(sunxi_mc_smp_cluster_cache_enable)
    15		/*
    16		* Enable cluster-level coherency, in preparation for turning on the MMU.
    17		*
    18		* Also enable regional clock gating and L2 data latency settings for
    19		* Cortex-A15. These settings are from the vendor kernel.
    20		*/
    21		mrc	p15, 0, r1, c0, c0, 0
  > 22		movw	r2, #(0xff00fff0&0xffff)
  > 23		movt	r2, #(0xff00fff0>>16)
    24		and	r1, r1, r2
    25		movw	r2, #(0x4100c0f0&0xffff)
    26		movt	r2, #(0x4100c0f0>>16)
    27		cmp	r1, r2
    28		bne	not_a15
    29	
    30		/* The following is Cortex-A15 specific */
    31	
    32		/* ACTLR2: Enable CPU regional clock gates */
    33		mrc p15, 1, r1, c15, c0, 4
    34		orr r1, r1, #(0x1<<31)
    35		mcr p15, 1, r1, c15, c0, 4
    36	
    37		/* L2ACTLR */
    38		mrc p15, 1, r1, c15, c0, 0
    39		/* Enable L2, GIC, and Timer regional clock gates */
    40		orr r1, r1, #(0x1<<26)
    41		/* Disable clean/evict from being pushed to external */
    42		orr r1, r1, #(0x1<<3)
    43		mcr p15, 1, r1, c15, c0, 0
    44	
    45		/* L2CTRL: L2 data RAM latency */
    46		mrc p15, 1, r1, c9, c0, 2
    47		bic r1, r1, #(0x7<<0)
    48		orr r1, r1, #(0x3<<0)
    49		mcr p15, 1, r1, c9, c0, 2
    50	
    51		/* End of Cortex-A15 specific setup */
    52		not_a15:
    53	
    54		/* Get value of sunxi_mc_smp_first_comer */
    55		adr	r1, first
    56		ldr	r0, [r1]
    57		ldr	r0, [r1, r0]
    58	
    59		/* Skip cci_enable_port_for_self if not first comer */
    60		cmp	r0, #0
    61		bxeq	lr
    62		b	cci_enable_port_for_self
    63	
    64		.align 2
    65		first: .word sunxi_mc_smp_first_comer - .
    66	ENDPROC(sunxi_mc_smp_cluster_cache_enable)
    67	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Mylène Josserand March 1, 2018, 8:21 a.m. UTC | #3 
Hello,

On Fri, 23 Feb 2018 16:09:49 +0100
Maxime Ripard <maxime.ripard@bootlin.com> wrote:

> On Fri, Feb 23, 2018 at 02:37:40PM +0100, Mylène Josserand wrote:
> > Move the assembly code for cluster cache enabling
> > into an assembly file instead of having it directly in C code.
> > 
> > Create a sunxi_boot entry that will perform a cluster cached
> > enabling and called secondary_startup.
> > 
> > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com>
> > ---
> >  arch/arm/mach-sunxi/Makefile  |  1 +
> >  arch/arm/mach-sunxi/headsmp.S | 73 +++++++++++++++++++++++++++++++++++++++++
> >  arch/arm/mach-sunxi/mc_smp.c  | 76 ++++---------------------------------------
> >  3 files changed, 80 insertions(+), 70 deletions(-)
> >  create mode 100644 arch/arm/mach-sunxi/headsmp.S
> > 
> > diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> > index 7de9cc286d53..d1a072b879ed 100644
> > --- a/arch/arm/mach-sunxi/Makefile
> > +++ b/arch/arm/mach-sunxi/Makefile
> > @@ -1,5 +1,6 @@
> >  CFLAGS_mc_smp.o	+= -march=armv7-a
> >  
> >  obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> > +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
> >  obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
> >  obj-$(CONFIG_SMP) += platsmp.o
> > diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> > new file mode 100644
> > index 000000000000..4f5957a6e188
> > --- /dev/null
> > +++ b/arch/arm/mach-sunxi/headsmp.S
> > @@ -0,0 +1,73 @@
> > +/*
> > + * SMP support for sunxi based systems with Cortex A7/A15
> > + *
> > + * Copyright (C) 2018 Bootlin  
> 
> This is just a copy, and while you can claim that you are one of the
> copyrights holder, you are not the sole one and the original author
> should be there.

yep, sorry about that.

> 
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.  
> 
> You want to use SPDX there instead.

Sure, I will update it.

> 
> > + */
> > +
> > +#include <linux/linkage.h>
> > +#include <asm/assembler.h>
> > +
> > +ENTRY(sunxi_mc_smp_cluster_cache_enable)
> > +	/*
> > +	* Enable cluster-level coherency, in preparation for turning on the MMU.
> > +	*
> > +	* Also enable regional clock gating and L2 data latency settings for
> > +	* Cortex-A15. These settings are from the vendor kernel.
> > +	*/  
> 
> The indentation is not correct there, the * should be aligned

Okay

> 
> > +	mrc	p15, 0, r1, c0, c0, 0
> > +	movw	r2, #(0xff00fff0&0xffff)
> > +	movt	r2, #(0xff00fff0>>16)  
> 
> This used to be defines, we should keep them, and we should have
> spaces around the operators as well.

Okay 

> 
> > +	and	r1, r1, r2
> > +	movw	r2, #(0x4100c0f0&0xffff)
> > +	movt	r2, #(0x4100c0f0>>16)
> > +	cmp	r1, r2
> > +	bne	not_a15
> > +
> > +	/* The following is Cortex-A15 specific */
> > +
> > +	/* ACTLR2: Enable CPU regional clock gates */
> > +	mrc p15, 1, r1, c15, c0, 4
> > +	orr r1, r1, #(0x1<<31)
> > +	mcr p15, 1, r1, c15, c0, 4
> > +
> > +	/* L2ACTLR */
> > +	mrc p15, 1, r1, c15, c0, 0
> > +	/* Enable L2, GIC, and Timer regional clock gates */
> > +	orr r1, r1, #(0x1<<26)
> > +	/* Disable clean/evict from being pushed to external */
> > +	orr r1, r1, #(0x1<<3)
> > +	mcr p15, 1, r1, c15, c0, 0
> > +
> > +	/* L2CTRL: L2 data RAM latency */
> > +	mrc p15, 1, r1, c9, c0, 2
> > +	bic r1, r1, #(0x7<<0)
> > +	orr r1, r1, #(0x3<<0)
> > +	mcr p15, 1, r1, c9, c0, 2
> > +
> > +	/* End of Cortex-A15 specific setup */
> > +	not_a15:
> > +
> > +	/* Get value of sunxi_mc_smp_first_comer */
> > +	adr	r1, first
> > +	ldr	r0, [r1]
> > +	ldr	r0, [r1, r0]
> > +
> > +	/* Skip cci_enable_port_for_self if not first comer */
> > +	cmp	r0, #0
> > +	bxeq	lr
> > +	b	cci_enable_port_for_self
> > +
> > +	.align 2
> > +	first: .word sunxi_mc_smp_first_comer - .
> > +ENDPROC(sunxi_mc_smp_cluster_cache_enable)
> > +
> > +#ifdef CONFIG_SMP  
> 
> I guess that whole file should be compiled only if we have SMP
> enabled.

True, thanks

> 
> > +ENTRY(sunxi_boot)
> > +	bl	sunxi_mc_smp_cluster_cache_enable
> > +	b	secondary_startup
> > +ENDPROC(sunxi_boot)
> > +#endif
> > diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> > index f2c2cfca28cd..4e807cc11a0f 100644
> > --- a/arch/arm/mach-sunxi/mc_smp.c
> > +++ b/arch/arm/mach-sunxi/mc_smp.c
> > @@ -82,6 +82,9 @@ static void __iomem *prcm_base;
> >  static void __iomem *sram_b_smp_base;
> >  static bool is_sun9i;
> >  
> > +extern void sunxi_boot(void);  
> 
> Why did you change the name of that function? The older one made it
> more obvious to tell what is going on.

Okay, I will use the old name.

> 
> > +extern void sunxi_cluster_cache_enable(void);  
> 
> Is that used somewhere?

No, I will remove it.

> 
> Thanks!
> Maxime
> 

Thanks,

Mylène
diff mbox

Patch

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..d1a072b879ed 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,6 @@ 
 CFLAGS_mc_smp.o	+= -march=armv7-a
 
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
 obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 000000000000..4f5957a6e188
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,73 @@ 
+/*
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ * Copyright (C) 2018 Bootlin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+	/*
+	* Enable cluster-level coherency, in preparation for turning on the MMU.
+	*
+	* Also enable regional clock gating and L2 data latency settings for
+	* Cortex-A15. These settings are from the vendor kernel.
+	*/
+	mrc	p15, 0, r1, c0, c0, 0
+	movw	r2, #(0xff00fff0&0xffff)
+	movt	r2, #(0xff00fff0>>16)
+	and	r1, r1, r2
+	movw	r2, #(0x4100c0f0&0xffff)
+	movt	r2, #(0x4100c0f0>>16)
+	cmp	r1, r2
+	bne	not_a15
+
+	/* The following is Cortex-A15 specific */
+
+	/* ACTLR2: Enable CPU regional clock gates */
+	mrc p15, 1, r1, c15, c0, 4
+	orr r1, r1, #(0x1<<31)
+	mcr p15, 1, r1, c15, c0, 4
+
+	/* L2ACTLR */
+	mrc p15, 1, r1, c15, c0, 0
+	/* Enable L2, GIC, and Timer regional clock gates */
+	orr r1, r1, #(0x1<<26)
+	/* Disable clean/evict from being pushed to external */
+	orr r1, r1, #(0x1<<3)
+	mcr p15, 1, r1, c15, c0, 0
+
+	/* L2CTRL: L2 data RAM latency */
+	mrc p15, 1, r1, c9, c0, 2
+	bic r1, r1, #(0x7<<0)
+	orr r1, r1, #(0x3<<0)
+	mcr p15, 1, r1, c9, c0, 2
+
+	/* End of Cortex-A15 specific setup */
+	not_a15:
+
+	/* Get value of sunxi_mc_smp_first_comer */
+	adr	r1, first
+	ldr	r0, [r1]
+	ldr	r0, [r1, r0]
+
+	/* Skip cci_enable_port_for_self if not first comer */
+	cmp	r0, #0
+	bxeq	lr
+	b	cci_enable_port_for_self
+
+	.align 2
+	first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+#ifdef CONFIG_SMP
+ENTRY(sunxi_boot)
+	bl	sunxi_mc_smp_cluster_cache_enable
+	b	secondary_startup
+ENDPROC(sunxi_boot)
+#endif
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index f2c2cfca28cd..4e807cc11a0f 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -82,6 +82,9 @@  static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 static bool is_sun9i;
 
+extern void sunxi_boot(void);
+extern void sunxi_cluster_cache_enable(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
 	struct device_node *node;
@@ -361,74 +364,7 @@  static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-	asm volatile (
-		"mrc	p15, 0, r1, c0, c0, 0\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_MASK & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-		"and	r1, r1, r2\n"
-		"movw	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0xffff) "\n"
-		"movt	r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-		"cmp	r1, r2\n"
-		"bne	not_a15\n"
-
-		/* The following is Cortex-A15 specific */
-
-		/* ACTLR2: Enable CPU regional clock gates */
-		"mrc p15, 1, r1, c15, c0, 4\n"
-		"orr r1, r1, #(0x1<<31)\n"
-		"mcr p15, 1, r1, c15, c0, 4\n"
-
-		/* L2ACTLR */
-		"mrc p15, 1, r1, c15, c0, 0\n"
-		/* Enable L2, GIC, and Timer regional clock gates */
-		"orr r1, r1, #(0x1<<26)\n"
-		/* Disable clean/evict from being pushed to external */
-		"orr r1, r1, #(0x1<<3)\n"
-		"mcr p15, 1, r1, c15, c0, 0\n"
-
-		/* L2CTRL: L2 data RAM latency */
-		"mrc p15, 1, r1, c9, c0, 2\n"
-		"bic r1, r1, #(0x7<<0)\n"
-		"orr r1, r1, #(0x3<<0)\n"
-		"mcr p15, 1, r1, c9, c0, 2\n"
-
-		/* End of Cortex-A15 specific setup */
-		"not_a15:\n"
-
-		/* Get value of sunxi_mc_smp_first_comer */
-		"adr	r1, first\n"
-		"ldr	r0, [r1]\n"
-		"ldr	r0, [r1, r0]\n"
-
-		/* Skip cci_enable_port_for_self if not first comer */
-		"cmp	r0, #0\n"
-		"bxeq	lr\n"
-		"b	cci_enable_port_for_self\n"
-
-		".align 2\n"
-		"first: .word sunxi_mc_smp_first_comer - .\n"
-	);
-}
-
-static void __naked sunxi_mc_smp_secondary_startup(void)
-{
-	asm volatile(
-		"bl	sunxi_mc_smp_cluster_cache_enable\n"
-		"b	secondary_startup"
-		/* Let compiler know about sunxi_mc_smp_cluster_cache_enable */
-		:: "i" (sunxi_mc_smp_cluster_cache_enable)
-	);
-}
+int sunxi_mc_smp_first_comer;
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -951,10 +887,10 @@  static int __init sunxi_mc_smp_init(void)
 
 	/* Set the hardware entry point address */
 	if (is_sun9i)
-		writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
+		writel(__pa_symbol(sunxi_boot),
 		       prcm_base + PRCM_CPU_SOFT_ENTRY_REG);
 	else
-		writel(__pa_symbol(sunxi_mc_smp_secondary_startup),
+		writel(__pa_symbol(sunxi_boot),
 		       r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG);
 
 	/* Actually enable multi cluster SMP */