| Message ID | 1520578651-28849-3-git-send-email-gabriel.fernandez@st.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Fri, Mar 09, 2018 at 07:57:31AM +0100, gabriel.fernandez@st.com wrote: > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > This patch adds DSI clock for STM32F469 board > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > --- > drivers/clk/clk-stm32f4.c | 11 ++++++++++- > include/dt-bindings/clock/stm32fx-clock.h | 3 ++- > 2 files changed, 12 insertions(+), 2 deletions(-) Reviewed-by: Rob Herring <robh@kernel.org> > > diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c > index 96c6b6b..d15bae6 100644 > --- a/drivers/clk/clk-stm32f4.c > +++ b/drivers/clk/clk-stm32f4.c > @@ -521,7 +521,7 @@ struct stm32f4_pll_data { > }; > > static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { > - { PLL, 50, { "pll", "pll-q", NULL } }, > + { PLL, 50, { "pll", "pll-q", "pll-r" } }, > { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, > { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, > }; > @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, > "no-clock", "lse", "lsi", "hse-rtc" > }; > > +static const char *dsi_parent[2] = { NULL, "pll-r" }; > + > static const char *lcd_parent[1] = { "pllsai-r-div" }; > > static const char *i2s_parents[2] = { "plli2s-r", NULL }; > @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data { > NO_GATE, 0, > 0 > }, > + { > + CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent), > + STM32F4_RCC_DCKCFGR, 29, 1, > + STM32F4_RCC_APB2ENR, 27, > + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT > + }, > }; > > static const struct stm32_aux_clk stm32f746_aux_clk[] = { > @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) > stm32f4_gate_map = data->gates_map; > > hse_clk = of_clk_get_parent_name(np, 0); > + dsi_parent[0] = hse_clk; > > i2s_in_clk = of_clk_get_parent_name(np, 1); > > diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h > index 4d523b0..58d8b51 100644 > --- a/include/dt-bindings/clock/stm32fx-clock.h > +++ b/include/dt-bindings/clock/stm32fx-clock.h > @@ -35,8 +35,9 @@ > #define CLK_SAIQ_PDIV 13 > #define CLK_HSI 14 > #define CLK_SYSCLK 15 > +#define CLK_F469_DSI 16 > > -#define END_PRIMARY_CLK 16 > +#define END_PRIMARY_CLK 17 > > #define CLK_HDMI_CEC 16 > #define CLK_SPDIF 17 > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Quoting gabriel.fernandez@st.com (2018-03-08 22:57:31) > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > This patch adds DSI clock for STM32F469 board > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > --- Applied to clk-next -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
VGhhbmtzIFN0ZXBoZW4gIQ0KDQpCZXN0IFJlZ2FyZHMNCg0KR2FicmllbA0KDQoNCk9uIDAzLzE5 LzIwMTggMDk6NDUgUE0sIFN0ZXBoZW4gQm95ZCB3cm90ZToNCj4gUXVvdGluZyBnYWJyaWVsLmZl cm5hbmRlekBzdC5jb20gKDIwMTgtMDMtMDggMjI6NTc6MzEpDQo+PiBGcm9tOiBHYWJyaWVsIEZl cm5hbmRleiA8Z2FicmllbC5mZXJuYW5kZXpAc3QuY29tPg0KPj4NCj4+IFRoaXMgcGF0Y2ggYWRk cyBEU0kgY2xvY2sgZm9yIFNUTTMyRjQ2OSBib2FyZA0KPj4NCj4+IFNpZ25lZC1vZmYtYnk6IEdh YnJpZWwgRmVybmFuZGV6IDxnYWJyaWVsLmZlcm5hbmRlekBzdC5jb20+DQo+PiAtLS0NCj4gQXBw bGllZCB0byBjbGstbmV4dA0KPg0K -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 96c6b6b..d15bae6 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -521,7 +521,7 @@ struct stm32f4_pll_data { }; static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { - { PLL, 50, { "pll", "pll-q", NULL } }, + { PLL, 50, { "pll", "pll-q", "pll-r" } }, { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, }; @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name, "no-clock", "lse", "lsi", "hse-rtc" }; +static const char *dsi_parent[2] = { NULL, "pll-r" }; + static const char *lcd_parent[1] = { "pllsai-r-div" }; static const char *i2s_parents[2] = { "plli2s-r", NULL }; @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data { NO_GATE, 0, 0 }, + { + CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent), + STM32F4_RCC_DCKCFGR, 29, 1, + STM32F4_RCC_APB2ENR, 27, + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT + }, }; static const struct stm32_aux_clk stm32f746_aux_clk[] = { @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np) stm32f4_gate_map = data->gates_map; hse_clk = of_clk_get_parent_name(np, 0); + dsi_parent[0] = hse_clk; i2s_in_clk = of_clk_get_parent_name(np, 1); diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 4d523b0..58d8b51 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -35,8 +35,9 @@ #define CLK_SAIQ_PDIV 13 #define CLK_HSI 14 #define CLK_SYSCLK 15 +#define CLK_F469_DSI 16 -#define END_PRIMARY_CLK 16 +#define END_PRIMARY_CLK 17 #define CLK_HDMI_CEC 16 #define CLK_SPDIF 17