Message ID | 1522160607-7104-1-git-send-email-abel.vesa@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Hi Abel, On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote: > From: Dong Aisheng <b29396@freescale.com> > > For init on clocks we should move it at the first place in imx7d_clocks_init() > before any clock operations, else the clock operation may fail in case the clock > is still not on. > > Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> > Signed-off-by: Dong Aisheng <b29396@freescale.com> > Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Thanks for your patches. You sent 4 patches today touching the same file. Please annotate the sequence of the patches (1/4, 2/4, etc) so that the maintainer can clearly know the order the patches should be applied.
Hi Fabio, On Tue, Mar 27, 2018 at 12:08:39PM -0300, Fabio Estevam wrote: > Hi Abel, > > On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote: > > From: Dong Aisheng <b29396@freescale.com> > > > > For init on clocks we should move it at the first place in imx7d_clocks_init() > > before any clock operations, else the clock operation may fail in case the clock > > is still not on. > > > > Acked-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> > > Signed-off-by: Dong Aisheng <b29396@freescale.com> > > Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com> > > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > > Thanks for your patches. > > You sent 4 patches today touching the same file. > > Please annotate the sequence of the patches (1/4, 2/4, etc) so that > the maintainer can clearly know the order the patches should be > applied. Yep, my bad. I'll resend as a patchset now.
Hi Abel, On Tue, Mar 27, 2018 at 11:23 AM, Abel Vesa <abel.vesa@nxp.com> wrote: > From: Dong Aisheng <b29396@freescale.com> > > For init on clocks we should move it at the first place in imx7d_clocks_init() > before any clock operations, else the clock operation may fail in case the clock > is still not on. The patch and the commit log does not match. You are not moving the code block to the "first place" inside imx7d_clocks_init(), so this is confusing. Also, why does this need to be done only in the imx7d clock driver?
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 89bfa75..9b17805 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -433,13 +433,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); - clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); - clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); - clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); - clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); - clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); - clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); - clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); @@ -886,6 +879,13 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); + clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); + clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); + clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); + clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); + clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); + clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); + /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);