| Message ID | 1521763162-11424-1-git-send-email-yaodong.li@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Jackie Li (2018-03-23 01:59:22) > GuC Address Space and WOPCM Layout diagrams won't be generated correctly by > sphinx build if not using proper reST syntax. > > This patch uses reST literal blocks to make sure GuC Address Space and > WOPCM Layout diagrams to be generated correctly, and it also corrects some > errors in the diagram description. > > v2: > - Fixed errors in diagram description > > v3: > - Updated GuC Address Space kernel-doc based on Michal's suggestion > > v4: > - Added WOPCM layout and GuC address space docs into i915.rst (Joonas) > > Signed-off-by: Jackie Li <yaodong.li@intel.com> > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Looks good. Thanks for the patch, I'll proceed to merge it. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Regards, Joonas > --- > Documentation/gpu/i915.rst | 15 ++++++++++ > drivers/gpu/drm/i915/intel_guc.c | 56 ++++++++++++++++++++------------------ > drivers/gpu/drm/i915/intel_wopcm.c | 44 ++++++++++++++++-------------- > 3 files changed, 67 insertions(+), 48 deletions(-) > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > index 41dc881..7ecad71 100644 > --- a/Documentation/gpu/i915.rst > +++ b/Documentation/gpu/i915.rst > @@ -335,6 +335,15 @@ objects, which has the goal to make space in gpu virtual address spaces. > .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c > :internal: > > +WOPCM > +===== > + > +WOPCM Layout > +------------ > + > +.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c > + :doc: WOPCM Layout > + > GuC > === > > @@ -359,6 +368,12 @@ GuC Firmware Layout > .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h > :doc: GuC Firmware Layout > > +GuC Address Space > +----------------- > + > +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c > + :doc: GuC Address Space > + > Tracing > ======= > > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c > index 8f93f5b..c5f64c7 100644 > --- a/drivers/gpu/drm/i915/intel_guc.c > +++ b/drivers/gpu/drm/i915/intel_guc.c > @@ -494,35 +494,37 @@ int intel_guc_resume(struct intel_guc *guc) > /** > * DOC: GuC Address Space > * > - * The layout of GuC address space is shown as below: > + * The layout of GuC address space is shown below: > * > - * +==============> +====================+ <== GUC_GGTT_TOP > - * ^ | | > - * | | | > - * | | DRAM | > - * | | Memory | > - * | | | > - * GuC | | > - * Address +========> +====================+ <== WOPCM Top > - * Space ^ | HW contexts RSVD | > - * | | | WOPCM | > - * | | +==> +--------------------+ <== GuC WOPCM Top > - * | GuC ^ | | > - * | GGTT | | | > - * | Pin GuC | GuC | > - * | Bias WOPCM | WOPCM | > - * | | Size | | > - * | | | | | > - * v v v | | > - * +=====+=====+==> +====================+ <== GuC WOPCM Base > - * | Non-GuC WOPCM | > - * | (HuC/Reserved) | > - * +====================+ <== WOPCM Base > + * :: > * > - * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of > - * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of > - * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is > - * set in GUC_WOPCM_SIZE register. > + * +==============> +====================+ <== GUC_GGTT_TOP > + * ^ | | > + * | | | > + * | | DRAM | > + * | | Memory | > + * | | | > + * GuC | | > + * Address +========> +====================+ <== WOPCM Top > + * Space ^ | HW contexts RSVD | > + * | | | WOPCM | > + * | | +==> +--------------------+ <== GuC WOPCM Top > + * | GuC ^ | | > + * | GGTT | | | > + * | Pin GuC | GuC | > + * | Bias WOPCM | WOPCM | > + * | | Size | | > + * | | | | | > + * v v v | | > + * +=====+=====+==> +====================+ <== GuC WOPCM Base > + * | Non-GuC WOPCM | > + * | (HuC/Reserved) | > + * +====================+ <== WOPCM Base > + * > + * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM > + * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped > + * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and > + * actual GuC WOPCM size. > */ > > /** > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c > index 4117886..74bf76f 100644 > --- a/drivers/gpu/drm/i915/intel_wopcm.c > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -11,28 +11,30 @@ > * DOC: WOPCM Layout > * > * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and > - * offset registers whose are calculated are determined by size of HuC/GuC > - * firmware size and set of hw requirements/restrictions as shown below: > + * offset registers whose values are calculated and determined by HuC/GuC > + * firmware size and set of hardware requirements/restrictions as shown below: > * > - * +=========> +====================+ <== WOPCM Top > - * ^ | HW contexts RSVD | > - * | +===> +====================+ <== GuC WOPCM Top > - * | ^ | | > - * | | | | > - * | | | | > - * | GuC | | > - * | WOPCM | | > - * | Size +--------------------+ > - * WOPCM | | GuC FW RSVD | > - * | | +--------------------+ > - * | | | GuC Stack RSVD | > - * | | +------------------- + > - * | v | GuC WOPCM RSVD | > - * | +===> +====================+ <== GuC WOPCM base > - * | | WOPCM RSVD | > - * | +------------------- + <== HuC Firmware Top > - * v | HuC FW | > - * +=========> +====================+ <== WOPCM Base > + * :: > + * > + * +=========> +====================+ <== WOPCM Top > + * ^ | HW contexts RSVD | > + * | +===> +====================+ <== GuC WOPCM Top > + * | ^ | | > + * | | | | > + * | | | | > + * | GuC | | > + * | WOPCM | | > + * | Size +--------------------+ > + * WOPCM | | GuC FW RSVD | > + * | | +--------------------+ > + * | | | GuC Stack RSVD | > + * | | +------------------- + > + * | v | GuC WOPCM RSVD | > + * | +===> +====================+ <== GuC WOPCM base > + * | | WOPCM RSVD | > + * | +------------------- + <== HuC Firmware Top > + * v | HuC FW | > + * +=========> +====================+ <== WOPCM Base > * > * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. > * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 > -- > 2.7.4 >
Quoting Joonas Lahtinen (2018-03-28 14:27:19) > Quoting Jackie Li (2018-03-23 01:59:22) > > GuC Address Space and WOPCM Layout diagrams won't be generated correctly by > > sphinx build if not using proper reST syntax. > > > > This patch uses reST literal blocks to make sure GuC Address Space and > > WOPCM Layout diagrams to be generated correctly, and it also corrects some > > errors in the diagram description. > > > > v2: > > - Fixed errors in diagram description > > > > v3: > > - Updated GuC Address Space kernel-doc based on Michal's suggestion > > > > v4: > > - Added WOPCM layout and GuC address space docs into i915.rst (Joonas) > > > > Signed-off-by: Jackie Li <yaodong.li@intel.com> > > Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> > > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > Looks good. Thanks for the patch, I'll proceed to merge it. For future reference, please use a single canonical name in patches (especially the Signed-off-by: field as it is the most important one: https://www.kernel.org/doc/html/v4.13/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin ). It'll also help when looking at the statistics, too. In this case our S-o-b checking tool complained that the patch author has not signed off their work (due to the difference in writing). Regards, Joonas > > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > Regards, Joonas > > > --- > > Documentation/gpu/i915.rst | 15 ++++++++++ > > drivers/gpu/drm/i915/intel_guc.c | 56 ++++++++++++++++++++------------------ > > drivers/gpu/drm/i915/intel_wopcm.c | 44 ++++++++++++++++-------------- > > 3 files changed, 67 insertions(+), 48 deletions(-) > > > > diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst > > index 41dc881..7ecad71 100644 > > --- a/Documentation/gpu/i915.rst > > +++ b/Documentation/gpu/i915.rst > > @@ -335,6 +335,15 @@ objects, which has the goal to make space in gpu virtual address spaces. > > .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c > > :internal: > > > > +WOPCM > > +===== > > + > > +WOPCM Layout > > +------------ > > + > > +.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c > > + :doc: WOPCM Layout > > + > > GuC > > === > > > > @@ -359,6 +368,12 @@ GuC Firmware Layout > > .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h > > :doc: GuC Firmware Layout > > > > +GuC Address Space > > +----------------- > > + > > +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c > > + :doc: GuC Address Space > > + > > Tracing > > ======= > > > > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c > > index 8f93f5b..c5f64c7 100644 > > --- a/drivers/gpu/drm/i915/intel_guc.c > > +++ b/drivers/gpu/drm/i915/intel_guc.c > > @@ -494,35 +494,37 @@ int intel_guc_resume(struct intel_guc *guc) > > /** > > * DOC: GuC Address Space > > * > > - * The layout of GuC address space is shown as below: > > + * The layout of GuC address space is shown below: > > * > > - * +==============> +====================+ <== GUC_GGTT_TOP > > - * ^ | | > > - * | | | > > - * | | DRAM | > > - * | | Memory | > > - * | | | > > - * GuC | | > > - * Address +========> +====================+ <== WOPCM Top > > - * Space ^ | HW contexts RSVD | > > - * | | | WOPCM | > > - * | | +==> +--------------------+ <== GuC WOPCM Top > > - * | GuC ^ | | > > - * | GGTT | | | > > - * | Pin GuC | GuC | > > - * | Bias WOPCM | WOPCM | > > - * | | Size | | > > - * | | | | | > > - * v v v | | > > - * +=====+=====+==> +====================+ <== GuC WOPCM Base > > - * | Non-GuC WOPCM | > > - * | (HuC/Reserved) | > > - * +====================+ <== WOPCM Base > > + * :: > > * > > - * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of > > - * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of > > - * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is > > - * set in GUC_WOPCM_SIZE register. > > + * +==============> +====================+ <== GUC_GGTT_TOP > > + * ^ | | > > + * | | | > > + * | | DRAM | > > + * | | Memory | > > + * | | | > > + * GuC | | > > + * Address +========> +====================+ <== WOPCM Top > > + * Space ^ | HW contexts RSVD | > > + * | | | WOPCM | > > + * | | +==> +--------------------+ <== GuC WOPCM Top > > + * | GuC ^ | | > > + * | GGTT | | | > > + * | Pin GuC | GuC | > > + * | Bias WOPCM | WOPCM | > > + * | | Size | | > > + * | | | | | > > + * v v v | | > > + * +=====+=====+==> +====================+ <== GuC WOPCM Base > > + * | Non-GuC WOPCM | > > + * | (HuC/Reserved) | > > + * +====================+ <== WOPCM Base > > + * > > + * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM > > + * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped > > + * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and > > + * actual GuC WOPCM size. > > */ > > > > /** > > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c > > index 4117886..74bf76f 100644 > > --- a/drivers/gpu/drm/i915/intel_wopcm.c > > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > > @@ -11,28 +11,30 @@ > > * DOC: WOPCM Layout > > * > > * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and > > - * offset registers whose are calculated are determined by size of HuC/GuC > > - * firmware size and set of hw requirements/restrictions as shown below: > > + * offset registers whose values are calculated and determined by HuC/GuC > > + * firmware size and set of hardware requirements/restrictions as shown below: > > * > > - * +=========> +====================+ <== WOPCM Top > > - * ^ | HW contexts RSVD | > > - * | +===> +====================+ <== GuC WOPCM Top > > - * | ^ | | > > - * | | | | > > - * | | | | > > - * | GuC | | > > - * | WOPCM | | > > - * | Size +--------------------+ > > - * WOPCM | | GuC FW RSVD | > > - * | | +--------------------+ > > - * | | | GuC Stack RSVD | > > - * | | +------------------- + > > - * | v | GuC WOPCM RSVD | > > - * | +===> +====================+ <== GuC WOPCM base > > - * | | WOPCM RSVD | > > - * | +------------------- + <== HuC Firmware Top > > - * v | HuC FW | > > - * +=========> +====================+ <== WOPCM Base > > + * :: > > + * > > + * +=========> +====================+ <== WOPCM Top > > + * ^ | HW contexts RSVD | > > + * | +===> +====================+ <== GuC WOPCM Top > > + * | ^ | | > > + * | | | | > > + * | | | | > > + * | GuC | | > > + * | WOPCM | | > > + * | Size +--------------------+ > > + * WOPCM | | GuC FW RSVD | > > + * | | +--------------------+ > > + * | | | GuC Stack RSVD | > > + * | | +------------------- + > > + * | v | GuC WOPCM RSVD | > > + * | +===> +====================+ <== GuC WOPCM base > > + * | | WOPCM RSVD | > > + * | +------------------- + <== HuC Firmware Top > > + * v | HuC FW | > > + * +=========> +====================+ <== WOPCM Base > > * > > * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. > > * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6 > > -- > > 2.7.4 > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 41dc881..7ecad71 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -335,6 +335,15 @@ objects, which has the goal to make space in gpu virtual address spaces. .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_shrinker.c :internal: +WOPCM +===== + +WOPCM Layout +------------ + +.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c + :doc: WOPCM Layout + GuC === @@ -359,6 +368,12 @@ GuC Firmware Layout .. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h :doc: GuC Firmware Layout +GuC Address Space +----------------- + +.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c + :doc: GuC Address Space + Tracing ======= diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 8f93f5b..c5f64c7 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -494,35 +494,37 @@ int intel_guc_resume(struct intel_guc *guc) /** * DOC: GuC Address Space * - * The layout of GuC address space is shown as below: + * The layout of GuC address space is shown below: * - * +==============> +====================+ <== GUC_GGTT_TOP - * ^ | | - * | | | - * | | DRAM | - * | | Memory | - * | | | - * GuC | | - * Address +========> +====================+ <== WOPCM Top - * Space ^ | HW contexts RSVD | - * | | | WOPCM | - * | | +==> +--------------------+ <== GuC WOPCM Top - * | GuC ^ | | - * | GGTT | | | - * | Pin GuC | GuC | - * | Bias WOPCM | WOPCM | - * | | Size | | - * | | | | | - * v v v | | - * +=====+=====+==> +====================+ <== GuC WOPCM Base - * | Non-GuC WOPCM | - * | (HuC/Reserved) | - * +====================+ <== WOPCM Base + * :: * - * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of - * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of - * the GuC ggtt_pin_bias is determined by the actually GuC WOPCM size which is - * set in GUC_WOPCM_SIZE register. + * +==============> +====================+ <== GUC_GGTT_TOP + * ^ | | + * | | | + * | | DRAM | + * | | Memory | + * | | | + * GuC | | + * Address +========> +====================+ <== WOPCM Top + * Space ^ | HW contexts RSVD | + * | | | WOPCM | + * | | +==> +--------------------+ <== GuC WOPCM Top + * | GuC ^ | | + * | GGTT | | | + * | Pin GuC | GuC | + * | Bias WOPCM | WOPCM | + * | | Size | | + * | | | | | + * v v v | | + * +=====+=====+==> +====================+ <== GuC WOPCM Base + * | Non-GuC WOPCM | + * | (HuC/Reserved) | + * +====================+ <== WOPCM Base + * + * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM + * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped + * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and + * actual GuC WOPCM size. */ /** diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 4117886..74bf76f 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -11,28 +11,30 @@ * DOC: WOPCM Layout * * The layout of the WOPCM will be fixed after writing to GuC WOPCM size and - * offset registers whose are calculated are determined by size of HuC/GuC - * firmware size and set of hw requirements/restrictions as shown below: + * offset registers whose values are calculated and determined by HuC/GuC + * firmware size and set of hardware requirements/restrictions as shown below: * - * +=========> +====================+ <== WOPCM Top - * ^ | HW contexts RSVD | - * | +===> +====================+ <== GuC WOPCM Top - * | ^ | | - * | | | | - * | | | | - * | GuC | | - * | WOPCM | | - * | Size +--------------------+ - * WOPCM | | GuC FW RSVD | - * | | +--------------------+ - * | | | GuC Stack RSVD | - * | | +------------------- + - * | v | GuC WOPCM RSVD | - * | +===> +====================+ <== GuC WOPCM base - * | | WOPCM RSVD | - * | +------------------- + <== HuC Firmware Top - * v | HuC FW | - * +=========> +====================+ <== WOPCM Base + * :: + * + * +=========> +====================+ <== WOPCM Top + * ^ | HW contexts RSVD | + * | +===> +====================+ <== GuC WOPCM Top + * | ^ | | + * | | | | + * | | | | + * | GuC | | + * | WOPCM | | + * | Size +--------------------+ + * WOPCM | | GuC FW RSVD | + * | | +--------------------+ + * | | | GuC Stack RSVD | + * | | +------------------- + + * | v | GuC WOPCM RSVD | + * | +===> +====================+ <== GuC WOPCM base + * | | WOPCM RSVD | + * | +------------------- + <== HuC Firmware Top + * v | HuC FW | + * +=========> +====================+ <== WOPCM Base * * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
GuC Address Space and WOPCM Layout diagrams won't be generated correctly by sphinx build if not using proper reST syntax. This patch uses reST literal blocks to make sure GuC Address Space and WOPCM Layout diagrams to be generated correctly, and it also corrects some errors in the diagram description. v2: - Fixed errors in diagram description v3: - Updated GuC Address Space kernel-doc based on Michal's suggestion v4: - Added WOPCM layout and GuC address space docs into i915.rst (Joonas) Signed-off-by: Jackie Li <yaodong.li@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> --- Documentation/gpu/i915.rst | 15 ++++++++++ drivers/gpu/drm/i915/intel_guc.c | 56 ++++++++++++++++++++------------------ drivers/gpu/drm/i915/intel_wopcm.c | 44 ++++++++++++++++-------------- 3 files changed, 67 insertions(+), 48 deletions(-)