| Message ID | 20180405114915.29609-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > Inside the psr work function, we want to wait for PSR to idle first > and > wish to do so without blocking the normal modeset path, so we do so > without holding the PSR lock. However, we first have to find which > pipe > PSR was enabled on, which requires chasing into the PSR struct and > requires locking to prevent intel_psr_disable() from concurrently > setting our pointer to NULL. > > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode") > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Durgadoss R <durgadoss.r@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: <stable@vger.kernel.org> # v4.0+ Feel free to add: Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++--------- > ---------- > 1 file changed, 44 insertions(+), 38 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 2d53f7398a6d..69a5b276f4d8 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp > *intel_dp, > cancel_delayed_work_sync(&dev_priv->psr.work); > } > > -static void intel_psr_work(struct work_struct *work) > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) > { > - struct drm_i915_private *dev_priv = > - container_of(work, typeof(*dev_priv), > psr.work.work); > - struct intel_dp *intel_dp = dev_priv->psr.enabled; > - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)- > >base.base.crtc; > - enum pipe pipe = to_intel_crtc(crtc)->pipe; > + struct intel_dp *intel_dp; nitpick: Why not already set it? struct intel_dp *intel_dp = dev_priv->psr.enabled; > + i915_reg_t reg; > + u32 mask; > + int err; > + > + intel_dp = dev_priv->psr.enabled; > + if (!intel_dp) > + return false; > > - /* We have to make sure PSR is ready for re-enable > - * otherwise it keeps disabled until next full > enable/disable cycle. > - * PSR might take some time to get fully disabled > - * and be ready for re-enable. > - */ > if (HAS_DDI(dev_priv)) { nitpick: While on that you could replace this for: if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) { > if (dev_priv->psr.psr2_enabled) { > - if (intel_wait_for_register(dev_priv, > - EDP_PSR2_STATUS, > - EDP_PSR2_STATUS_ > STATE_MASK, > - 0, > - 50)) { > - DRM_ERROR("Timed out waiting for > PSR2 Idle for re-enable\n"); > - return; > - } > + reg = EDP_PSR2_STATUS; > + mask = EDP_PSR2_STATUS_STATE_MASK; > } else { > - if (intel_wait_for_register(dev_priv, > - EDP_PSR_STATUS, > - EDP_PSR_STATUS_S > TATE_MASK, > - 0, > - 50)) { > - DRM_ERROR("Timed out waiting for PSR > Idle for re-enable\n"); > - return; > - } > + reg = EDP_PSR_STATUS; > + mask = EDP_PSR_STATUS_STATE_MASK; > } > } else { > - if (intel_wait_for_register(dev_priv, > - VLV_PSRSTAT(pipe), > - VLV_EDP_PSR_IN_TRANS, > - 0, > - 1)) { > - DRM_ERROR("Timed out waiting for PSR Idle > for re-enable\n"); > - return; > - } > + struct drm_crtc *crtc = > + dp_to_dig_port(intel_dp)->base.base.crtc; > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > + > + reg = VLV_PSRSTAT(pipe); > + mask = VLV_EDP_PSR_IN_TRANS; > } > + > + mutex_unlock(&dev_priv->psr.lock); > + > + err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); > + if (err) > + DRM_ERROR("Timed out waiting for PSR Idle for re- > enable\n"); > + > + /* After the unlocked wait, verify that PSR is still wanted! > */ > mutex_lock(&dev_priv->psr.lock); > - intel_dp = dev_priv->psr.enabled; > + return err == 0 && dev_priv->psr.enabled; > +} > > - if (!intel_dp) > +static void intel_psr_work(struct work_struct *work) > +{ > + struct drm_i915_private *dev_priv = > + container_of(work, typeof(*dev_priv), > psr.work.work); > + > + mutex_lock(&dev_priv->psr.lock); > + > + /* > + * We have to make sure PSR is ready for re-enable > + * otherwise it keeps disabled until next full > enable/disable cycle. > + * PSR might take some time to get fully disabled > + * and be ready for re-enable. > + */ > + if (!psr_wait_for_idle(dev_priv)) > goto unlock; > > /* > @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct > *work) > if (dev_priv->psr.busy_frontbuffer_bits) > goto unlock; > > - intel_psr_activate(intel_dp); > + intel_psr_activate(dev_priv->psr.enabled); > unlock: > mutex_unlock(&dev_priv->psr.lock); > }
On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > Inside the psr work function, we want to wait for PSR to idle first > > and > > wish to do so without blocking the normal modeset path, so we do so > > without holding the PSR lock. However, we first have to find which > > pipe > > PSR was enabled on, which requires chasing into the PSR struct and > > requires locking to prevent intel_psr_disable() from concurrently > > setting our pointer to NULL. > > > > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode") > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Durgadoss R <durgadoss.r@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: <stable@vger.kernel.org> # v4.0+ > > Feel free to add: > Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com> > > > --- > > drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++--------- > > ---------- > > 1 file changed, 44 insertions(+), 38 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 2d53f7398a6d..69a5b276f4d8 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp > > *intel_dp, > > cancel_delayed_work_sync(&dev_priv->psr.work); > > } > > > > -static void intel_psr_work(struct work_struct *work) > > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) > > { > > - struct drm_i915_private *dev_priv = > > - container_of(work, typeof(*dev_priv), > > psr.work.work); > > - struct intel_dp *intel_dp = dev_priv->psr.enabled; > > - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)- > > >base.base.crtc; > > - enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + struct intel_dp *intel_dp; > > nitpick: Why not already set it? > struct intel_dp *intel_dp = dev_priv->psr.enabled; > > > > + i915_reg_t reg; > > + u32 mask; > > + int err; > > + > > + intel_dp = dev_priv->psr.enabled; > > + if (!intel_dp) > > + return false; > > > > - /* We have to make sure PSR is ready for re-enable > > - * otherwise it keeps disabled until next full > > enable/disable cycle. > > - * PSR might take some time to get fully disabled > > - * and be ready for re-enable. > > - */ > > if (HAS_DDI(dev_priv)) { > > > nitpick: While on that you could replace this for: > > if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) { > > > if (dev_priv->psr.psr2_enabled) { > > - if (intel_wait_for_register(dev_priv, > > - EDP_PSR2_STATUS, > > - EDP_PSR2_STATUS_ > > STATE_MASK, > > - 0, > > - 50)) { > > - DRM_ERROR("Timed out waiting for > > PSR2 Idle for re-enable\n"); > > - return; > > - } > > + reg = EDP_PSR2_STATUS; > > + mask = EDP_PSR2_STATUS_STATE_MASK; > > } else { > > - if (intel_wait_for_register(dev_priv, > > - EDP_PSR_STATUS, > > - EDP_PSR_STATUS_S > > TATE_MASK, > > - 0, > > - 50)) { > > - DRM_ERROR("Timed out waiting for PSR > > Idle for re-enable\n"); > > - return; > > - } > > + reg = EDP_PSR_STATUS; > > + mask = EDP_PSR_STATUS_STATE_MASK; > > } > > } else { > > - if (intel_wait_for_register(dev_priv, > > - VLV_PSRSTAT(pipe), > > - VLV_EDP_PSR_IN_TRANS, > > - 0, > > - 1)) { > > - DRM_ERROR("Timed out waiting for PSR Idle > > for re-enable\n"); > > - return; > > - } > > + struct drm_crtc *crtc = > > + dp_to_dig_port(intel_dp)->base.base.crtc; I'm afraid that the issue is this pointer here. So this will only mask the issue. Should we maybe stash the pipe? :/ > > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + > > + reg = VLV_PSRSTAT(pipe); > > + mask = VLV_EDP_PSR_IN_TRANS; > > } > > + > > + mutex_unlock(&dev_priv->psr.lock); > > + > > + err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); > > + if (err) > > + DRM_ERROR("Timed out waiting for PSR Idle for re- > > enable\n"); > > + > > + /* After the unlocked wait, verify that PSR is still wanted! > > */ > > mutex_lock(&dev_priv->psr.lock); > > - intel_dp = dev_priv->psr.enabled; > > + return err == 0 && dev_priv->psr.enabled; > > +} > > > > - if (!intel_dp) > > +static void intel_psr_work(struct work_struct *work) > > +{ > > + struct drm_i915_private *dev_priv = > > + container_of(work, typeof(*dev_priv), > > psr.work.work); > > + > > + mutex_lock(&dev_priv->psr.lock); > > + > > + /* > > + * We have to make sure PSR is ready for re-enable > > + * otherwise it keeps disabled until next full > > enable/disable cycle. > > + * PSR might take some time to get fully disabled > > + * and be ready for re-enable. > > + */ > > + if (!psr_wait_for_idle(dev_priv)) > > goto unlock; > > > > /* > > @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct > > *work) > > if (dev_priv->psr.busy_frontbuffer_bits) > > goto unlock; > > > > - intel_psr_activate(intel_dp); > > + intel_psr_activate(dev_priv->psr.enabled); > > unlock: > > mutex_unlock(&dev_priv->psr.lock); > > }
Quoting Rodrigo Vivi (2018-04-06 23:18:16) > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > > + struct drm_crtc *crtc = > > > + dp_to_dig_port(intel_dp)->base.base.crtc; > > I'm afraid that the issue is this pointer here. So this will only mask > the issue. > > Should we maybe stash the pipe? :/ It's not that bad. pipe cannot change until after psr_disable is called, right? And psr_disable ensures that this worker is flushed. The current problem is just the coordination of cancelling the worker, where we may set psr.enabled to NULL right before the worker grabs it and dereferences it. So if we lock until we have the pipe, we know that dereference chain is valid, and we know that psr_disable() cannot complete until we complete the wait. So the pipe remains valid until we return (so long as the pipe exists when we start). -Chris
On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote: > Quoting Rodrigo Vivi (2018-04-06 23:18:16) > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > > > + struct drm_crtc *crtc = > > > > + dp_to_dig_port(intel_dp)->base.base.crtc; > > > > I'm afraid that the issue is this pointer here. So this will only mask > > the issue. > > > > Should we maybe stash the pipe? :/ > > It's not that bad. pipe cannot change until after psr_disable is called, > right? And psr_disable ensures that this worker is flushed. The current > problem is just the coordination of cancelling the worker, where we may > set psr.enabled to NULL right before the worker grabs it and > dereferences it. > > So if we lock until we have the pipe, we know that dereference chain is > valid, and we know that psr_disable() cannot complete until we complete > the wait. So the pipe remains valid until we return (so long as the pipe > exists when we start). hmm... it makes sense and I have no better suggestion actually. So, as long it really fixes the regression we introduced: Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > -Chris > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Souza, Jose (2018-04-06 19:12:27) > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > Inside the psr work function, we want to wait for PSR to idle first > > and > > wish to do so without blocking the normal modeset path, so we do so > > without holding the PSR lock. However, we first have to find which > > pipe > > PSR was enabled on, which requires chasing into the PSR struct and > > requires locking to prevent intel_psr_disable() from concurrently > > setting our pointer to NULL. > > > > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode") > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Durgadoss R <durgadoss.r@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: <stable@vger.kernel.org> # v4.0+ > > Feel free to add: > Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com> > > > --- > > drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++--------- > > ---------- > > 1 file changed, 44 insertions(+), 38 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 2d53f7398a6d..69a5b276f4d8 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp > > *intel_dp, > > cancel_delayed_work_sync(&dev_priv->psr.work); > > } > > > > -static void intel_psr_work(struct work_struct *work) > > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) > > { > > - struct drm_i915_private *dev_priv = > > - container_of(work, typeof(*dev_priv), > > psr.work.work); > > - struct intel_dp *intel_dp = dev_priv->psr.enabled; > > - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)- > > >base.base.crtc; > > - enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + struct intel_dp *intel_dp; > > nitpick: Why not already set it? > struct intel_dp *intel_dp = dev_priv->psr.enabled; I have a very strong personal preference for coupling logic together and not splitting it up into an early init and later test. It certainly helps against falling into the trap of using the variable inside the init block before you test. > > + i915_reg_t reg; > > + u32 mask; > > + int err; > > + > > + intel_dp = dev_priv->psr.enabled; > > + if (!intel_dp) > > + return false; > > > > - /* We have to make sure PSR is ready for re-enable > > - * otherwise it keeps disabled until next full > > enable/disable cycle. > > - * PSR might take some time to get fully disabled > > - * and be ready for re-enable. > > - */ > > if (HAS_DDI(dev_priv)) { > > > nitpick: While on that you could replace this for: > > if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) { That I leave to others ;) Though I would suggest making the branch around the VLV_PSRSTAT(pipe) explicit as that is only applicable to a subset, and easier to extend as we typically end up with if (GEN >= 10) { } else if (bxt_special_case_1) { } else if (GEN >= 8) { } else if (vlv_or_chv_special_case_2) { } else if (GEN >= 6) { } else { MISSING_CASE(); } or whatever is required. -Chris
Quoting Rodrigo Vivi (2018-04-09 20:14:32) > On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote: > > Quoting Rodrigo Vivi (2018-04-06 23:18:16) > > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > > > > + struct drm_crtc *crtc = > > > > > + dp_to_dig_port(intel_dp)->base.base.crtc; > > > > > > I'm afraid that the issue is this pointer here. So this will only mask > > > the issue. > > > > > > Should we maybe stash the pipe? :/ > > > > It's not that bad. pipe cannot change until after psr_disable is called, > > right? And psr_disable ensures that this worker is flushed. The current > > problem is just the coordination of cancelling the worker, where we may > > set psr.enabled to NULL right before the worker grabs it and > > dereferences it. > > > > So if we lock until we have the pipe, we know that dereference chain is > > valid, and we know that psr_disable() cannot complete until we complete > > the wait. So the pipe remains valid until we return (so long as the pipe > > exists when we start). > > hmm... it makes sense and I have no better suggestion actually. > So, as long it really fixes the regression we introduced: > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> It does fix the abstract race, but I have no evidence of this being hit in practice. Pushed, but up to you if you care about this being backported. Note this race is different from the GPF CI reported. Hmm, I think https://bugs.freedesktop.org/show_bug.cgi?id=105959 is the same one as hit on the kasan run earlier. -Chris
On Tue, Apr 10, 2018 at 12:00:26PM +0100, Chris Wilson wrote: > Quoting Rodrigo Vivi (2018-04-09 20:14:32) > > On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote: > > > Quoting Rodrigo Vivi (2018-04-06 23:18:16) > > > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > > > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > > > > > + struct drm_crtc *crtc = > > > > > > + dp_to_dig_port(intel_dp)->base.base.crtc; > > > > > > > > I'm afraid that the issue is this pointer here. So this will only mask > > > > the issue. > > > > > > > > Should we maybe stash the pipe? :/ > > > > > > It's not that bad. pipe cannot change until after psr_disable is called, > > > right? And psr_disable ensures that this worker is flushed. The current > > > problem is just the coordination of cancelling the worker, where we may > > > set psr.enabled to NULL right before the worker grabs it and > > > dereferences it. > > > > > > So if we lock until we have the pipe, we know that dereference chain is > > > valid, and we know that psr_disable() cannot complete until we complete > > > the wait. So the pipe remains valid until we return (so long as the pipe > > > exists when we start). > > > > hmm... it makes sense and I have no better suggestion actually. > > So, as long it really fixes the regression we introduced: > > > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > It does fix the abstract race, but I have no evidence of this being hit > in practice. Pushed, but up to you if you care about this being > backported. > > Note this race is different from the GPF CI reported. Hmm, I think > https://bugs.freedesktop.org/show_bug.cgi?id=105959 is the same one as > hit on the kasan run earlier. Ouch, thanks for the clarification... I was really considering that this was the case... but I should have noticed that there was no bugzilla referenced here... > -Chris > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2d53f7398a6d..69a5b276f4d8 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp *intel_dp, cancel_delayed_work_sync(&dev_priv->psr.work); } -static void intel_psr_work(struct work_struct *work) +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = - container_of(work, typeof(*dev_priv), psr.work.work); - struct intel_dp *intel_dp = dev_priv->psr.enabled; - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; - enum pipe pipe = to_intel_crtc(crtc)->pipe; + struct intel_dp *intel_dp; + i915_reg_t reg; + u32 mask; + int err; + + intel_dp = dev_priv->psr.enabled; + if (!intel_dp) + return false; - /* We have to make sure PSR is ready for re-enable - * otherwise it keeps disabled until next full enable/disable cycle. - * PSR might take some time to get fully disabled - * and be ready for re-enable. - */ if (HAS_DDI(dev_priv)) { if (dev_priv->psr.psr2_enabled) { - if (intel_wait_for_register(dev_priv, - EDP_PSR2_STATUS, - EDP_PSR2_STATUS_STATE_MASK, - 0, - 50)) { - DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n"); - return; - } + reg = EDP_PSR2_STATUS; + mask = EDP_PSR2_STATUS_STATE_MASK; } else { - if (intel_wait_for_register(dev_priv, - EDP_PSR_STATUS, - EDP_PSR_STATUS_STATE_MASK, - 0, - 50)) { - DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); - return; - } + reg = EDP_PSR_STATUS; + mask = EDP_PSR_STATUS_STATE_MASK; } } else { - if (intel_wait_for_register(dev_priv, - VLV_PSRSTAT(pipe), - VLV_EDP_PSR_IN_TRANS, - 0, - 1)) { - DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); - return; - } + struct drm_crtc *crtc = + dp_to_dig_port(intel_dp)->base.base.crtc; + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + reg = VLV_PSRSTAT(pipe); + mask = VLV_EDP_PSR_IN_TRANS; } + + mutex_unlock(&dev_priv->psr.lock); + + err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); + if (err) + DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); + + /* After the unlocked wait, verify that PSR is still wanted! */ mutex_lock(&dev_priv->psr.lock); - intel_dp = dev_priv->psr.enabled; + return err == 0 && dev_priv->psr.enabled; +} - if (!intel_dp) +static void intel_psr_work(struct work_struct *work) +{ + struct drm_i915_private *dev_priv = + container_of(work, typeof(*dev_priv), psr.work.work); + + mutex_lock(&dev_priv->psr.lock); + + /* + * We have to make sure PSR is ready for re-enable + * otherwise it keeps disabled until next full enable/disable cycle. + * PSR might take some time to get fully disabled + * and be ready for re-enable. + */ + if (!psr_wait_for_idle(dev_priv)) goto unlock; /* @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct *work) if (dev_priv->psr.busy_frontbuffer_bits) goto unlock; - intel_psr_activate(intel_dp); + intel_psr_activate(dev_priv->psr.enabled); unlock: mutex_unlock(&dev_priv->psr.lock); }
Inside the psr work function, we want to wait for PSR to idle first and wish to do so without blocking the normal modeset path, so we do so without holding the PSR lock. However, we first have to find which pipe PSR was enabled on, which requires chasing into the PSR struct and requires locking to prevent intel_psr_disable() from concurrently setting our pointer to NULL. Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Durgadoss R <durgadoss.r@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: <stable@vger.kernel.org> # v4.0+ --- drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 38 deletions(-)