| Message ID | CAOuPqTFJABMcDHmQcNoNZioBBJ8RcreeevsRfh5b46ZgKZLetw@mail.gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 17 April 2018 at 22:32, Henry Wertz <hwertz10@gmail.com> wrote: > Please find submitted a patch for ARM memory barriers. This patch is > against qemu-2.12-rc2 but I do believe it should apply for anything from > 2.11.x to current. (the code being patched was added in for 2.11 series.) > > > I found with qemu 2.11.x or newer that I would get an illegal instruction > error running some Intel binaries on my ARM chromebook. On investigation, > I found it was quitting on memory barriers. > qemu instruction: > mb $0x31 > was translating as: > 0x604050cc: 5bf07ff5 blpl #0x600250a8 > > After patch it gives: > 0x604050cc: f57ff05b dmb ish > > In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be > correct based on online docs, but due to some endian-related shenanigans it > had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier > for ARMv6) also should be byte swapped (and this patch does so). > I have not checked for correctness of aarch64's barrier instruction. > > Signed-off-by: Henry Wertz <hwertz10@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Richard, did you want to take this via the tcg tree? thanks -- PMM
On 04/17/2018 11:51 AM, Peter Maydell wrote: > On 17 April 2018 at 22:32, Henry Wertz <hwertz10@gmail.com> wrote: >> Please find submitted a patch for ARM memory barriers. This patch is >> against qemu-2.12-rc2 but I do believe it should apply for anything from >> 2.11.x to current. (the code being patched was added in for 2.11 series.) >> >> >> I found with qemu 2.11.x or newer that I would get an illegal instruction >> error running some Intel binaries on my ARM chromebook. On investigation, >> I found it was quitting on memory barriers. >> qemu instruction: >> mb $0x31 >> was translating as: >> 0x604050cc: 5bf07ff5 blpl #0x600250a8 >> >> After patch it gives: >> 0x604050cc: f57ff05b dmb ish >> >> In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be >> correct based on online docs, but due to some endian-related shenanigans it >> had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier >> for ARMv6) also should be byte swapped (and this patch does so). >> I have not checked for correctness of aarch64's barrier instruction. >> >> Signed-off-by: Henry Wertz <hwertz10@gmail.com> > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > Richard, did you want to take this via the tcg tree? Yes, I can do that. r~
*** tcg/arm/tcg-target.inc.c.orig 2018-04-04 15:28:50.000000000 -0500 --- tcg/arm/tcg-target.inc.c 2018-04-16 12:55:04.917518898 -0500 *************** *** 158,167 **** INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, ! INSN_DMB_ISH = 0x5bf07ff5, ! INSN_DMB_MCR = 0xba0f07ee, /* Architected nop introduced in v6k. */ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this also Just So Happened to do nothing on pre-v6k so that we --- 158,167 ---- INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, ! INSN_DMB_ISH = 0xf57ff05b, ! INSN_DMB_MCR = 0xee070fba, /* Architected nop introduced in v6k. */ /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this also Just So Happened to do nothing on pre-v6k so that we
Please find submitted a patch for ARM memory barriers. This patch is against qemu-2.12-rc2 but I do believe it should apply for anything from 2.11.x to current. (the code being patched was added in for 2.11 series.) I found with qemu 2.11.x or newer that I would get an illegal instruction error running some Intel binaries on my ARM chromebook. On investigation, I found it was quitting on memory barriers. qemu instruction: mb $0x31 was translating as: 0x604050cc: 5bf07ff5 blpl #0x600250a8 After patch it gives: 0x604050cc: f57ff05b dmb ish In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be correct based on online docs, but due to some endian-related shenanigans it had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory barrier for ARMv6) also should be byte swapped (and this patch does so). I have not checked for correctness of aarch64's barrier instruction. Signed-off-by: Henry Wertz <hwertz10@gmail.com>