| Message ID | 20180421164246.8477-3-miquel.raynal@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Sat, Apr 21, 2018 at 06:42:46PM +0200, Miquel Raynal wrote: > The Nintendo NES/SuperNES features an R16 already well supported in > mainline. > > The console over UART0 may be wired on two ports of the R16, both > available on the NES Classic PCB. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 + > .../boot/dts/sun8i-r16-nintendo-nes-classic.dts | 56 ++++++++++++++++++++++ > .../dts/sun8i-r16-nintendo-super-nes-classic.dts | 19 ++++++++ > 4 files changed, 79 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts > create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7e2424957809..6813abc8399a 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1010,6 +1010,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-h3-orangepi-plus.dtb \ > sun8i-h3-orangepi-plus2e.dtb \ > sun8i-r16-bananapi-m2m.dtb \ > + sun8i-r16-nintendo-nes-classic.dtb \ > + sun8i-r16-nintendo-supernes-classic.dtb \ This doesn't match your DTS name :) > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > index 6b9e85b4ba0f..44f3cad3de75 100644 > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > @@ -198,6 +198,8 @@ > clock-names = "ahb", "mod"; > resets = <&ccu RST_BUS_NAND>; > reset-names = "ahb"; > + pinctrl-names = "default"; > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; This should be in your first patch I guess? > diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > new file mode 100644 > index 000000000000..9cbe058feb6f > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: GPL-2.0 OR X11 > +/* Copyright (c) 2018 Miquèl RAYNAL <miquel.raynal@bootlin.com> */ > + > +/dts-v1/; > +#include "sun8i-r16-nintendo-nes-classic.dts" > + > +/ { > + model = "Nintendo SuperNES Classic Edition"; > + compatible = "nintendo,supernes-classic", "allwinner,sun8i-r16", We should have the same split in the compatible (ie, super-nes-classic) and we should probably add the nes-classic compatible in there as well. > + "allwinner,sun8i-a33"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; Isn't that part of the NES DTSI already? Maxime
Hi Maxime, On Mon, 23 Apr 2018 09:24:03 +0200, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > Hi, > > On Sat, Apr 21, 2018 at 06:42:46PM +0200, Miquel Raynal wrote: > > The Nintendo NES/SuperNES features an R16 already well supported in > > mainline. > > > > The console over UART0 may be wired on two ports of the R16, both > > available on the NES Classic PCB. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > > --- > > arch/arm/boot/dts/Makefile | 2 + > > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 + > > .../boot/dts/sun8i-r16-nintendo-nes-classic.dts | 56 ++++++++++++++++++++++ > > .../dts/sun8i-r16-nintendo-super-nes-classic.dts | 19 ++++++++ > > 4 files changed, 79 insertions(+) > > create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts > > create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > > > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > > index 7e2424957809..6813abc8399a 100644 > > --- a/arch/arm/boot/dts/Makefile > > +++ b/arch/arm/boot/dts/Makefile > > @@ -1010,6 +1010,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > > sun8i-h3-orangepi-plus.dtb \ > > sun8i-h3-orangepi-plus2e.dtb \ > > sun8i-r16-bananapi-m2m.dtb \ > > + sun8i-r16-nintendo-nes-classic.dtb \ > > + sun8i-r16-nintendo-supernes-classic.dtb \ > > This doesn't match your DTS name :) Ooooops /o\ > > > sun8i-r16-parrot.dtb \ > > sun8i-r40-bananapi-m2-ultra.dtb \ > > sun8i-v3s-licheepi-zero.dtb \ > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > @@ -198,6 +198,8 @@ > > clock-names = "ahb", "mod"; > > resets = <&ccu RST_BUS_NAND>; > > reset-names = "ahb"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > This should be in your first patch I guess? Actually I think this should not be there but instead, because it is board-related, these two lines should be in the nes-classic.dts' nfc node, right? Other a23/a33/r16 based designs could use the second set of CS/RB pins. > > > diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > > new file mode 100644 > > index 000000000000..9cbe058feb6f > > --- /dev/null > > +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts > > @@ -0,0 +1,19 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR X11 > > +/* Copyright (c) 2018 Miquèl RAYNAL <miquel.raynal@bootlin.com> */ > > + > > +/dts-v1/; > > +#include "sun8i-r16-nintendo-nes-classic.dts" > > + > > +/ { > > + model = "Nintendo SuperNES Classic Edition"; > > + compatible = "nintendo,supernes-classic", "allwinner,sun8i-r16", > > > We should have the same split in the compatible (ie, > super-nes-classic) and we should probably add the nes-classic > compatible in there as well. Sure. > > > + "allwinner,sun8i-a33"; > > + > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > Isn't that part of the NES DTSI already? Right, I was not sure if those two should be kept or not. Removed. > > Maxime > Thanks, Miquèl
On Mon, Apr 23, 2018 at 12:27:52PM +0200, Miquel Raynal wrote: > > > sun8i-r16-parrot.dtb \ > > > sun8i-r40-bananapi-m2-ultra.dtb \ > > > sun8i-v3s-licheepi-zero.dtb \ > > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > @@ -198,6 +198,8 @@ > > > clock-names = "ahb", "mod"; > > > resets = <&ccu RST_BUS_NAND>; > > > reset-names = "ahb"; > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > > > This should be in your first patch I guess? > > Actually I think this should not be there but instead, because it is > board-related, these two lines should be in the nes-classic.dts' nfc > node, right? Other a23/a33/r16 based designs could use the second set > of CS/RB pins. Does that ever happen? On a theoretical level, then yeah, sure. But if all the boards seen out there are using the same setup (which is pretty common), then there's no reason not to do it in the DTSI. Maxime
Hi Maxime, On Tue, 24 Apr 2018 09:55:05 +0200, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > On Mon, Apr 23, 2018 at 12:27:52PM +0200, Miquel Raynal wrote: > > > > sun8i-r16-parrot.dtb \ > > > > sun8i-r40-bananapi-m2-ultra.dtb \ > > > > sun8i-v3s-licheepi-zero.dtb \ > > > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > @@ -198,6 +198,8 @@ > > > > clock-names = "ahb", "mod"; > > > > resets = <&ccu RST_BUS_NAND>; > > > > reset-names = "ahb"; > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > > > > > This should be in your first patch I guess? > > > > Actually I think this should not be there but instead, because it is > > board-related, these two lines should be in the nes-classic.dts' nfc > > node, right? Other a23/a33/r16 based designs could use the second set > > of CS/RB pins. > > Does that ever happen? > > On a theoretical level, then yeah, sure. But if all the boards seen > out there are using the same setup (which is pretty common), then > there's no reason not to do it in the DTSI. Then I will add these two properties in the DTSI in the first patch. Thanks, Miquèl > > Maxime >
Hi Maxime, On Tue, 24 Apr 2018 09:55:05 +0200, Maxime Ripard <maxime.ripard@bootlin.com> wrote: > On Mon, Apr 23, 2018 at 12:27:52PM +0200, Miquel Raynal wrote: > > > > sun8i-r16-parrot.dtb \ > > > > sun8i-r40-bananapi-m2-ultra.dtb \ > > > > sun8i-v3s-licheepi-zero.dtb \ > > > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > @@ -198,6 +198,8 @@ > > > > clock-names = "ahb", "mod"; > > > > resets = <&ccu RST_BUS_NAND>; > > > > reset-names = "ahb"; > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > > > > > This should be in your first patch I guess? > > > > Actually I think this should not be there but instead, because it is > > board-related, these two lines should be in the nes-classic.dts' nfc > > node, right? Other a23/a33/r16 based designs could use the second set > > of CS/RB pins. > > Does that ever happen? > > On a theoretical level, then yeah, sure. But if all the boards seen > out there are using the same setup (which is pretty common), then > there's no reason not to do it in the DTSI. I compared the various boards configurations [1] with the R16 datasheet [2], all the boards having a NAND configure all the related pins (including CS1 and RB1). So I guess I can put both properties in the DTSI. There is one case (sinlinx_sina33) where the NAND is not used and the pins are used for an alternate function: SPI0; but I guess this is not a problem as in this case, the NAND node would not exist in the resulting DTB. Regards, Miquèl > > Maxime >
On Tue, 24 Apr 2018 10:49:11 +0200, Miquel Raynal <miquel.raynal@bootlin.com> wrote: > Hi Maxime, > > On Tue, 24 Apr 2018 09:55:05 +0200, Maxime Ripard > <maxime.ripard@bootlin.com> wrote: > > > On Mon, Apr 23, 2018 at 12:27:52PM +0200, Miquel Raynal wrote: > > > > > sun8i-r16-parrot.dtb \ > > > > > sun8i-r40-bananapi-m2-ultra.dtb \ > > > > > sun8i-v3s-licheepi-zero.dtb \ > > > > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > > > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > @@ -198,6 +198,8 @@ > > > > > clock-names = "ahb", "mod"; > > > > > resets = <&ccu RST_BUS_NAND>; > > > > > reset-names = "ahb"; > > > > > + pinctrl-names = "default"; > > > > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > > > > > > > This should be in your first patch I guess? > > > > > > Actually I think this should not be there but instead, because it is > > > board-related, these two lines should be in the nes-classic.dts' nfc > > > node, right? Other a23/a33/r16 based designs could use the second set > > > of CS/RB pins. > > > > Does that ever happen? > > > > On a theoretical level, then yeah, sure. But if all the boards seen > > out there are using the same setup (which is pretty common), then > > there's no reason not to do it in the DTSI. > > I compared the various boards configurations [1] with the R16 datasheet > [2], all the boards having a NAND configure all the related pins > (including CS1 and RB1). So I guess I can put both properties in the > DTSI. I forgot to add: [1] https://github.com/linux-sunxi/sunxi-boards/tree/master/sys_config/a33 [2] http://linux-sunxi.org/images/b/b3/R16_Datasheet_V1.4_%281%29.pdf Sorry for the spam :) Miquèl > > There is one case (sinlinx_sina33) where the NAND is not used and the > pins are used for an alternate function: SPI0; but I guess this is not > a problem as in this case, the NAND node would not exist in the > resulting DTB. > > Regards, > Miquèl >
On Tue, Apr 24, 2018 at 10:49:11AM +0200, Miquel Raynal wrote: > Hi Maxime, > > On Tue, 24 Apr 2018 09:55:05 +0200, Maxime Ripard > <maxime.ripard@bootlin.com> wrote: > > > On Mon, Apr 23, 2018 at 12:27:52PM +0200, Miquel Raynal wrote: > > > > > sun8i-r16-parrot.dtb \ > > > > > sun8i-r40-bananapi-m2-ultra.dtb \ > > > > > sun8i-v3s-licheepi-zero.dtb \ > > > > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > index 6b9e85b4ba0f..44f3cad3de75 100644 > > > > > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > > > > > @@ -198,6 +198,8 @@ > > > > > clock-names = "ahb", "mod"; > > > > > resets = <&ccu RST_BUS_NAND>; > > > > > reset-names = "ahb"; > > > > > + pinctrl-names = "default"; > > > > > + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; > > > > > > > > This should be in your first patch I guess? > > > > > > Actually I think this should not be there but instead, because it is > > > board-related, these two lines should be in the nes-classic.dts' nfc > > > node, right? Other a23/a33/r16 based designs could use the second set > > > of CS/RB pins. > > > > Does that ever happen? > > > > On a theoretical level, then yeah, sure. But if all the boards seen > > out there are using the same setup (which is pretty common), then > > there's no reason not to do it in the DTSI. > > I compared the various boards configurations [1] with the R16 datasheet > [2], all the boards having a NAND configure all the related pins > (including CS1 and RB1). So I guess I can put both properties in the > DTSI. I don't think we should until we have a clearer view of whether it's needed or not. If it turns out that they are not using it, and that we need to remove it from the DTSI, it's going to be a nightmare to track down what board actually needs what pin. > There is one case (sinlinx_sina33) where the NAND is not used and the > pins are used for an alternate function: SPI0; but I guess this is not > a problem as in this case, the NAND node would not exist in the > resulting DTB. Yeah, the sinA33 is using an eMMC, so it's not relevant here. Maxime
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e2424957809..6813abc8399a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1010,6 +1010,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-bananapi-m2m.dtb \ + sun8i-r16-nintendo-nes-classic.dtb \ + sun8i-r16-nintendo-supernes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 6b9e85b4ba0f..44f3cad3de75 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -198,6 +198,8 @@ clock-names = "ahb", "mod"; resets = <&ccu RST_BUS_NAND>; reset-names = "ahb"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts new file mode 100644 index 000000000000..fc0658cfa319 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* Copyright (c) 2016 FUKAUMI Naoki <naobsd@gmail.com> */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Nintendo NES Classic Edition"; + compatible = "nintendo,nes-classic", "allwinner,sun8i-r16", + "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + /* + * UART0 is available on two ports: PB and PF, both are accessible. + * PF can also be used for the SD card so PB is preferred. + */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&nfc { + status = "okay"; + + /* 2Gb Macronix MX30LF2G18AC (3V) */ + nand@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + /* VBUS is always on because it is wired to the power supply */ + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts new file mode 100644 index 000000000000..9cbe058feb6f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* Copyright (c) 2018 Miquèl RAYNAL <miquel.raynal@bootlin.com> */ + +/dts-v1/; +#include "sun8i-r16-nintendo-nes-classic.dts" + +/ { + model = "Nintendo SuperNES Classic Edition"; + compatible = "nintendo,supernes-classic", "allwinner,sun8i-r16", + "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +};
The Nintendo NES/SuperNES features an R16 already well supported in mainline. The console over UART0 may be wired on two ports of the R16, both available on the NES Classic PCB. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 + .../boot/dts/sun8i-r16-nintendo-nes-classic.dts | 56 ++++++++++++++++++++++ .../dts/sun8i-r16-nintendo-super-nes-classic.dts | 19 ++++++++ 4 files changed, 79 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-nes-classic.dts create mode 100644 arch/arm/boot/dts/sun8i-r16-nintendo-super-nes-classic.dts