| Message ID | 1525293261-13613-7-git-send-email-oscar.mateo@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Oscar Mateo <oscar.mateo@intel.com> writes: > Avoids an undefined LLC behavior. > > BSpec: 9613 > > v2: Renamed to Wa_1405733216 > v3: Spaces around '<<' and fix surrounding code > v4: Rebased on top of the WA refactoring > v5: Added References (Mika) > > References: HSDES#1405733216 > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 +++-- > drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a132980..845c7e4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7232,8 +7232,9 @@ enum { > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > #define GEN8_L3SQCREG4 _MMIO(0xb118) > -#define GEN8_LQSC_RO_PERF_DIS (1<<27) > -#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) > +#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) > +#define GEN8_LQSC_RO_PERF_DIS (1 << 27) > +#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) > > /* GEN8 chicken */ > #define HDC_CHICKEN0 _MMIO(0x7300) > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index 2bb5dad..b0babe8 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) > I915_WRITE(GEN11_GACB_PERF_CTRL, > ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) | > GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4)); > + > + /* Wa_1405733216:icl > + * Formerly known as WaDisableCleanEvicts > + */ > + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > + GEN11_LQSC_CLEAN_EVICT_DISABLE)); > } > > void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a132980..845c7e4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7232,8 +7232,9 @@ enum { #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) #define GEN8_L3SQCREG4 _MMIO(0xb118) -#define GEN8_LQSC_RO_PERF_DIS (1<<27) -#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21) +#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) +#define GEN8_LQSC_RO_PERF_DIS (1 << 27) +#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) /* GEN8 chicken */ #define HDC_CHICKEN0 _MMIO(0x7300) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 2bb5dad..b0babe8 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) I915_WRITE(GEN11_GACB_PERF_CTRL, ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) | GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4)); + + /* Wa_1405733216:icl + * Formerly known as WaDisableCleanEvicts + */ + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | + GEN11_LQSC_CLEAN_EVICT_DISABLE)); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
Avoids an undefined LLC behavior. BSpec: 9613 v2: Renamed to Wa_1405733216 v3: Spaces around '<<' and fix surrounding code v4: Rebased on top of the WA refactoring v5: Added References (Mika) References: HSDES#1405733216 Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-)