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[5/7] arm64: allwinner: h6: add R_INTC interrupt controller

Message ID 20180503183847.11046-6-icenowy@aosc.io (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Icenowy Zheng May 3, 2018, 6:38 p.m. UTC 
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.

Add it into the device tree.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Maxime Ripard May 4, 2018, 3:10 p.m. UTC | #1 
On Fri, May 04, 2018 at 02:38:45AM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
> A64 SoC, but has its base address changed due to the memory map change
> in H6.
> 
> Add it into the device tree.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied, thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index a18b78fb4850..b0b342c8c189 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -184,6 +184,15 @@ 
 			#reset-cells = <1>;
 		};
 
+		r_intc: interrupt-controller@7021000 {
+			compatible = "allwinner,sun50i-h6-r-intc",
+				     "allwinner,sun6i-a31-r-intc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x07021000 0x400>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		r_pio: pinctrl@7022000 {
 			compatible = "allwinner,sun50i-h6-r-pinctrl";
 			reg = <0x07022000 0x400>;