| Message ID | 1525293261-13613-13-git-send-email-oscar.mateo@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Oscar Mateo <oscar.mateo@intel.com> writes: > Disable CGPSF unit clock gating to prevent an issue. > > v2: Rebased on top of the WA refactoring > v3: Added References (Mika) > > References: HSDES#1406838659 > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++----- > drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f6a38fd..8caf42f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3838,15 +3838,18 @@ enum { > * GEN10 clock gating regs > */ > #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) > -#define SARBUNIT_CLKGATE_DIS (1 << 5) > -#define RCCUNIT_CLKGATE_DIS (1 << 7) > -#define MSCUNIT_CLKGATE_DIS (1 << 10) > +#define SARBUNIT_CLKGATE_DIS (1 << 5) > +#define RCCUNIT_CLKGATE_DIS (1 << 7) > +#define MSCUNIT_CLKGATE_DIS (1 << 10) > > #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) > -#define GWUNIT_CLKGATE_DIS (1 << 16) > +#define GWUNIT_CLKGATE_DIS (1 << 16) > > #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) > -#define VFUNIT_CLKGATE_DIS (1 << 20) > +#define VFUNIT_CLKGATE_DIS (1 << 20) Some unintentional whitespace movements? > + > +#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) > +#define CGPSF_CLKGATE_DIS (1 << 3) > > /* > * Display engine regs > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index bba43fd..35f2de3 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) > I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER, > (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) | > GEN11_I2M_WRITE_DISABLE)); > + > + /* Wa_1406838659:icl (pre-prod) */ > + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0)) It is inclusive and C0 is fixed so, IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0)) With that and whitespace on check, Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > + I915_WRITE(INF_UNIT_LEVEL_CLKGATE, > + (I915_READ(INF_UNIT_LEVEL_CLKGATE) | > + CGPSF_CLKGATE_DIS)); > } > > void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f6a38fd..8caf42f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3838,15 +3838,18 @@ enum { * GEN10 clock gating regs */ #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) -#define SARBUNIT_CLKGATE_DIS (1 << 5) -#define RCCUNIT_CLKGATE_DIS (1 << 7) -#define MSCUNIT_CLKGATE_DIS (1 << 10) +#define SARBUNIT_CLKGATE_DIS (1 << 5) +#define RCCUNIT_CLKGATE_DIS (1 << 7) +#define MSCUNIT_CLKGATE_DIS (1 << 10) #define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) -#define GWUNIT_CLKGATE_DIS (1 << 16) +#define GWUNIT_CLKGATE_DIS (1 << 16) #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) -#define VFUNIT_CLKGATE_DIS (1 << 20) +#define VFUNIT_CLKGATE_DIS (1 << 20) + +#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) +#define CGPSF_CLKGATE_DIS (1 << 3) /* * Display engine regs diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index bba43fd..35f2de3 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER, (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) | GEN11_I2M_WRITE_DISABLE)); + + /* Wa_1406838659:icl (pre-prod) */ + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0)) + I915_WRITE(INF_UNIT_LEVEL_CLKGATE, + (I915_READ(INF_UNIT_LEVEL_CLKGATE) | + CGPSF_CLKGATE_DIS)); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
Disable CGPSF unit clock gating to prevent an issue. v2: Rebased on top of the WA refactoring v3: Added References (Mika) References: HSDES#1406838659 Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++----- drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ 2 files changed, 14 insertions(+), 5 deletions(-)