| Message ID | 1525814984-20039-14-git-send-email-oscar.mateo@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Oscar Mateo <oscar.mateo@intel.com> writes: > Avoids a hang during soft reset. > > v2: Rebased on top of the WA refactoring > v3: Added References (Mika) > v4: > - Rebased > - C, not lisp (Chris) > - Which steppings affected by this are not clear. > For the moment, apply unconditionally as per the > BSpec (Mika) > - Add reference to another HSD also related > > References: HSDES#1405476379 > References: HSDES#2006612137 > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 +++++ > drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ce48427..1449178 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9897,6 +9897,11 @@ enum skl_power_gate { > /* Media decoder 2 MOCS registers */ > #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) > > +#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) > +#define PMFLUSHDONE_LNICRSDROP (1 << 20) > +#define PMFLUSH_GAPL3UNBLOCK (1 << 21) > +#define PMFLUSHDONE_LNEBLK (1 << 22) > + > /* gamt regs */ > #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) > #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index 942d322..5eec4ce 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) > I915_WRITE(INF_UNIT_LEVEL_CLKGATE, > I915_READ(INF_UNIT_LEVEL_CLKGATE) | > CGPSF_CLKGATE_DIS); > + > + /* WaForwardProgressSoftReset:icl */ > + I915_WRITE(GEN10_SCRATCH_LNCF2, > + I915_READ(GEN10_SCRATCH_LNCF2) | > + PMFLUSHDONE_LNICRSDROP | > + PMFLUSH_GAPL3UNBLOCK | > + PMFLUSHDONE_LNEBLK); > } > > void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce48427..1449178 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9897,6 +9897,11 @@ enum skl_power_gate { /* Media decoder 2 MOCS registers */ #define GEN11_MFX2_MOCS(i) _MMIO(0x10000 + (i) * 4) +#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) +#define PMFLUSHDONE_LNICRSDROP (1 << 20) +#define PMFLUSH_GAPL3UNBLOCK (1 << 21) +#define PMFLUSHDONE_LNEBLK (1 << 22) + /* gamt regs */ #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 942d322..5eec4ce 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -761,6 +761,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) I915_WRITE(INF_UNIT_LEVEL_CLKGATE, I915_READ(INF_UNIT_LEVEL_CLKGATE) | CGPSF_CLKGATE_DIS); + + /* WaForwardProgressSoftReset:icl */ + I915_WRITE(GEN10_SCRATCH_LNCF2, + I915_READ(GEN10_SCRATCH_LNCF2) | + PMFLUSHDONE_LNICRSDROP | + PMFLUSH_GAPL3UNBLOCK | + PMFLUSHDONE_LNEBLK); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
Avoids a hang during soft reset. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Which steppings affected by this are not clear. For the moment, apply unconditionally as per the BSpec (Mika) - Add reference to another HSD also related References: HSDES#1405476379 References: HSDES#2006612137 Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++ 2 files changed, 12 insertions(+)