| Message ID | 20180517170309.28630-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > All DDI platforms support the full set of preemph settings for each > supported vswing, so let's use the same code for them. We'll also move > the code into intel_ddi.c so that it sits closer to the actual buf trans > tables. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_dp.c | 30 ++++-------------------------- > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 26 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index b98ac0541f19..1665bc588241 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) > DP_TRAIN_VOLTAGE_SWING_MASK; > } > > +/* > + * We assume that the full set of pre-emphasis values can be > + * used on all DDI platforms. Should that change we need to > + * rethink this code. > + */ > +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) > +{ > + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > + return DP_TRAIN_PRE_EMPH_LEVEL_3; > + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: > + return DP_TRAIN_PRE_EMPH_LEVEL_2; > + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > + return DP_TRAIN_PRE_EMPH_LEVEL_1; > + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > + default: > + return DP_TRAIN_PRE_EMPH_LEVEL_0; > + } > +} > + > static void cnl_ddi_vswing_program(struct intel_encoder *encoder, > int level, enum intel_output_type type) > { > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 4755bb1b0b40..538b10084a9d 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3239,33 +3239,11 @@ uint8_t > intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) > { > struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); > - enum port port = dp_to_dig_port(intel_dp)->base.port; > + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; > + enum port port = encoder->port; > > - if (INTEL_GEN(dev_priv) >= 9) { > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > - return DP_TRAIN_PRE_EMPH_LEVEL_3; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: > - return DP_TRAIN_PRE_EMPH_LEVEL_2; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > - return DP_TRAIN_PRE_EMPH_LEVEL_1; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > - default: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > - } > - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > - return DP_TRAIN_PRE_EMPH_LEVEL_3; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: > - return DP_TRAIN_PRE_EMPH_LEVEL_2; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > - return DP_TRAIN_PRE_EMPH_LEVEL_1; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > - default: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > - } > + if (HAS_DDI(dev_priv)) { > + return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 12002fc77235..22af249393a4 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, > u32 bxt_signal_levels(struct intel_dp *intel_dp); > uint32_t ddi_signal_levels(struct intel_dp *intel_dp); > u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); > +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, > + u8 voltage_swing); > int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, > bool enable); > void icl_map_plls_to_ports(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b98ac0541f19..1665bc588241 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2115,6 +2115,26 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) DP_TRAIN_VOLTAGE_SWING_MASK; } +/* + * We assume that the full set of pre-emphasis values can be + * used on all DDI platforms. Should that change we need to + * rethink this code. + */ +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing) +{ + switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { + case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: + return DP_TRAIN_PRE_EMPH_LEVEL_3; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: + return DP_TRAIN_PRE_EMPH_LEVEL_2; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: + return DP_TRAIN_PRE_EMPH_LEVEL_1; + case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: + default: + return DP_TRAIN_PRE_EMPH_LEVEL_0; + } +} + static void cnl_ddi_vswing_program(struct intel_encoder *encoder, int level, enum intel_output_type type) { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 4755bb1b0b40..538b10084a9d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3239,33 +3239,11 @@ uint8_t intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) { struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); - enum port port = dp_to_dig_port(intel_dp)->base.port; + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + enum port port = encoder->port; - if (INTEL_GEN(dev_priv) >= 9) { - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: - return DP_TRAIN_PRE_EMPH_LEVEL_3; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: - return DP_TRAIN_PRE_EMPH_LEVEL_2; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: - return DP_TRAIN_PRE_EMPH_LEVEL_1; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: - return DP_TRAIN_PRE_EMPH_LEVEL_0; - default: - return DP_TRAIN_PRE_EMPH_LEVEL_0; - } - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: - return DP_TRAIN_PRE_EMPH_LEVEL_3; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: - return DP_TRAIN_PRE_EMPH_LEVEL_2; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: - return DP_TRAIN_PRE_EMPH_LEVEL_1; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: - default: - return DP_TRAIN_PRE_EMPH_LEVEL_0; - } + if (HAS_DDI(dev_priv)) { + return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 12002fc77235..22af249393a4 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1410,6 +1410,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, u32 bxt_signal_levels(struct intel_dp *intel_dp); uint32_t ddi_signal_levels(struct intel_dp *intel_dp); u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder); +u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, + u8 voltage_swing); int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, bool enable); void icl_map_plls_to_ports(struct drm_crtc *crtc,