diff mbox

[4/5] drm/i915: Rename SNB/IVB CPU eDP signal level funcs

Message ID 20180517170309.28630-4-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä May 17, 2018, 5:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To make the intent more clear, let's rename the signal level funcs for
the SNB/IVB CPU eDP.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Jani Nikula May 17, 2018, 5:48 p.m. UTC | #1 
On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To make the intent more clear, let's rename the signal level funcs for
> the SNB/IVB CPU eDP.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 263e4b1d1db9..cd4c60bfc4c2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
>  	return signal_levels;
>  }
>  
> -/* Gen6's DP voltage swing and pre-emphasis control */
> +/* SNB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen6_edp_signal_levels(uint8_t train_set)
> +snb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
>  	}
>  }
>  
> -/* Gen7's DP voltage swing and pre-emphasis control */
> +/* IVB CPU eDP voltage swing and pre-emphasis control */
>  static uint32_t
> -gen7_edp_signal_levels(uint8_t train_set)
> +ivb_cpu_edp_signal_levels(uint8_t train_set)
>  {
>  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
>  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		signal_levels = vlv_signal_levels(intel_dp);
>  	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> -		signal_levels = gen7_edp_signal_levels(train_set);
> +		signal_levels = ivb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
>  	} else if (IS_GEN6(dev_priv) && port == PORT_A) {

Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

Anyway,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> -		signal_levels = gen6_edp_signal_levels(train_set);
> +		signal_levels = snb_cpu_edp_signal_levels(train_set);
>  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
>  	} else {
>  		signal_levels = gen4_signal_levels(train_set);
Ville Syrjälä May 17, 2018, 5:50 p.m. UTC | #2 
On Thu, May 17, 2018 at 08:48:49PM +0300, Jani Nikula wrote:
> On Thu, 17 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > To make the intent more clear, let's rename the signal level funcs for
> > the SNB/IVB CPU eDP.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 263e4b1d1db9..cd4c60bfc4c2 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3488,9 +3488,9 @@ gen4_signal_levels(uint8_t train_set)
> >  	return signal_levels;
> >  }
> >  
> > -/* Gen6's DP voltage swing and pre-emphasis control */
> > +/* SNB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen6_edp_signal_levels(uint8_t train_set)
> > +snb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> >  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3516,9 +3516,9 @@ gen6_edp_signal_levels(uint8_t train_set)
> >  	}
> >  }
> >  
> > -/* Gen7's DP voltage swing and pre-emphasis control */
> > +/* IVB CPU eDP voltage swing and pre-emphasis control */
> >  static uint32_t
> > -gen7_edp_signal_levels(uint8_t train_set)
> > +ivb_cpu_edp_signal_levels(uint8_t train_set)
> >  {
> >  	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
> >  					 DP_TRAIN_PRE_EMPHASIS_MASK);
> > @@ -3566,10 +3566,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> >  	} else if (IS_VALLEYVIEW(dev_priv)) {
> >  		signal_levels = vlv_signal_levels(intel_dp);
> >  	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> > -		signal_levels = gen7_edp_signal_levels(train_set);
> > +		signal_levels = ivb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> >  	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
> 
> Should we use IS_SANDYBRIDGE() - which doesn't exist - here then...

I have considered adding IS_ILK and IS_SNB to make some of
the display code more consistent looking. But I never bothered
to actually write the patch.

> 
> Anyway,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> > -		signal_levels = gen6_edp_signal_levels(train_set);
> > +		signal_levels = snb_cpu_edp_signal_levels(train_set);
> >  		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> >  	} else {
> >  		signal_levels = gen4_signal_levels(train_set);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 263e4b1d1db9..cd4c60bfc4c2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3488,9 +3488,9 @@  gen4_signal_levels(uint8_t train_set)
 	return signal_levels;
 }
 
-/* Gen6's DP voltage swing and pre-emphasis control */
+/* SNB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen6_edp_signal_levels(uint8_t train_set)
+snb_cpu_edp_signal_levels(uint8_t train_set)
 {
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3516,9 +3516,9 @@  gen6_edp_signal_levels(uint8_t train_set)
 	}
 }
 
-/* Gen7's DP voltage swing and pre-emphasis control */
+/* IVB CPU eDP voltage swing and pre-emphasis control */
 static uint32_t
-gen7_edp_signal_levels(uint8_t train_set)
+ivb_cpu_edp_signal_levels(uint8_t train_set)
 {
 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
@@ -3566,10 +3566,10 @@  intel_dp_set_signal_levels(struct intel_dp *intel_dp)
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		signal_levels = vlv_signal_levels(intel_dp);
 	} else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
-		signal_levels = gen7_edp_signal_levels(train_set);
+		signal_levels = ivb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
 	} else if (IS_GEN6(dev_priv) && port == PORT_A) {
-		signal_levels = gen6_edp_signal_levels(train_set);
+		signal_levels = snb_cpu_edp_signal_levels(train_set);
 		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
 	} else {
 		signal_levels = gen4_signal_levels(train_set);