diff mbox

[26/24] drm/i915/icl: Add allowed DP rates for Icelake

Message ID 20180524234241.3665-2-paulo.r.zanoni@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Zanoni, Paulo R May 24, 2018, 11:42 p.m. UTC 
From: Manasi Navare <manasi.d.navare@intel.com>

For ICL, on Combo PHY the allowed max rates are:
 - HBR3 8.1 eDP (DDIA)
 - HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
 - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
 - DP on legacy connector - DDIC/D/E/F)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

Comments

James Ausmus May 25, 2018, 6:32 p.m. UTC | #1 
On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> For ICL, on Combo PHY the allowed max rates are:
>  - HBR3 8.1 eDP (DDIA)
>  - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
>  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
>  - DP on legacy connector - DDIC/D/E/F)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5109023abe28..3ee8e74cf2b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>  	return 810000;
>  }
>  
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum port port = dig_port->base.port;
> +
> +	/* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> +	 * and on Combo PHY Port B the maximum supported is HBR2.
> +	 */
> +	if (port == PORT_B)
> +		return 540000;
> +
> +	return 810000;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>  
> -	if (IS_CANNONLAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 10) {
>  		source_rates = cnl_rates;
>  		size = ARRAY_SIZE(cnl_rates);
> -		max_rate = cnl_max_source_rate(intel_dp);
> +		if (IS_ICELAKE(dev_priv))
> +			max_rate = icl_max_source_rate(intel_dp);
> +		else
> +			max_rate = cnl_max_source_rate(intel_dp);
>  	} else if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> -- 
> 2.14.3
>
Zanoni, Paulo R June 1, 2018, 11:43 p.m. UTC | #2 
Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> > 
> > For ICL, on Combo PHY the allowed max rates are:
> >  - HBR3 8.1 eDP (DDIA)
> >  - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> >  - DP on legacy connector - DDIC/D/E/F)
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> 
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> >  1 file changed, 19 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 5109023abe28..3ee8e74cf2b8 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > *intel_dp)
> >  	return 810000;
> >  }
> >  
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > +	enum port port = dig_port->base.port;
> > +
> > +	/* On Combo PHY port A max speed is HBR3 for all Vccio
> > voltages
> > +	 * and on Combo PHY Port B the maximum supported is HBR2.
> > +	 */
> > +	if (port == PORT_B)
> > +		return 540000;
> > +
> > +	return 810000;
> > +}
> > +
> >  static void
> >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> >  {
> > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > *intel_dp)
> >  	/* This should only be done once */
> >  	WARN_ON(intel_dp->source_rates || intel_dp-
> > >num_source_rates);
> >  
> > -	if (IS_CANNONLAKE(dev_priv)) {
> > +	if (INTEL_GEN(dev_priv) >= 10) {
> >  		source_rates = cnl_rates;
> >  		size = ARRAY_SIZE(cnl_rates);
> > -		max_rate = cnl_max_source_rate(intel_dp);
> > +		if (IS_ICELAKE(dev_priv))
> > +			max_rate = icl_max_source_rate(intel_dp);
> > +		else
> > +			max_rate = cnl_max_source_rate(intel_dp);

Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
any possible future platform would be using the ICL table instead of
the CNL one.


> >  	} else if (IS_GEN9_LP(dev_priv)) {
> >  		source_rates = bxt_rates;
> >  		size = ARRAY_SIZE(bxt_rates);
> > -- 
> > 2.14.3
> >
Rodrigo Vivi June 14, 2018, 7:23 p.m. UTC | #3 
On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> For ICL, on Combo PHY the allowed max rates are:
>  - HBR3 8.1 eDP (DDIA)
>  - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
>  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
>  - DP on legacy connector - DDIC/D/E/F)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5109023abe28..3ee8e74cf2b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>  	return 810000;
>  }
>  
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum port port = dig_port->base.port;
> +
> +	/* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> +	 * and on Combo PHY Port B the maximum supported is HBR2.
> +	 */
> +	if (port == PORT_B)

A more generic way here would be COMBO and !eDP

> +		return 540000;
> +
> +	return 810000;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>  
> -	if (IS_CANNONLAKE(dev_priv)) {
> +	if (INTEL_GEN(dev_priv) >= 10) {
>  		source_rates = cnl_rates;
>  		size = ARRAY_SIZE(cnl_rates);
> -		max_rate = cnl_max_source_rate(intel_dp);
> +		if (IS_ICELAKE(dev_priv))

and gen >= 11

but changes can be in follow-up work, so

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +			max_rate = icl_max_source_rate(intel_dp);
> +		else
> +			max_rate = cnl_max_source_rate(intel_dp);
>  	} else if (IS_GEN9_LP(dev_priv)) {
>  		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
> -- 
> 2.14.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Rodrigo Vivi June 14, 2018, 7:24 p.m. UTC | #4 
On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > 
> > > For ICL, on Combo PHY the allowed max rates are:
> > >  - HBR3 8.1 eDP (DDIA)
> > >  - HBR2 5.4 DisplayPort (DDIB)
> > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > >  - DP on legacy connector - DDIC/D/E/F)
> > > 
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > 
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 5109023abe28..3ee8e74cf2b8 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > *intel_dp)
> > >  	return 810000;
> > >  }
> > >  
> > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > +{
> > > +	struct intel_digital_port *dig_port =
> > > dp_to_dig_port(intel_dp);
> > > +	enum port port = dig_port->base.port;
> > > +
> > > +	/* On Combo PHY port A max speed is HBR3 for all Vccio
> > > voltages
> > > +	 * and on Combo PHY Port B the maximum supported is HBR2.
> > > +	 */
> > > +	if (port == PORT_B)
> > > +		return 540000;
> > > +
> > > +	return 810000;
> > > +}
> > > +
> > >  static void
> > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > >  {
> > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > *intel_dp)
> > >  	/* This should only be done once */
> > >  	WARN_ON(intel_dp->source_rates || intel_dp-
> > > >num_source_rates);
> > >  
> > > -	if (IS_CANNONLAKE(dev_priv)) {
> > > +	if (INTEL_GEN(dev_priv) >= 10) {
> > >  		source_rates = cnl_rates;
> > >  		size = ARRAY_SIZE(cnl_rates);
> > > -		max_rate = cnl_max_source_rate(intel_dp);
> > > +		if (IS_ICELAKE(dev_priv))
> > > +			max_rate = icl_max_source_rate(intel_dp);
> > > +		else
> > > +			max_rate = cnl_max_source_rate(intel_dp);
> 
> Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> any possible future platform would be using the ICL table instead of
> the CNL one.

I agree... but I'd prefer s/IS_ICELAKE/gen >= 11

> 
> 
> > >  	} else if (IS_GEN9_LP(dev_priv)) {
> > >  		source_rates = bxt_rates;
> > >  		size = ARRAY_SIZE(bxt_rates);
> > > -- 
> > > 2.14.3
> > > 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Navare, Manasi June 15, 2018, 12:45 a.m. UTC | #5 
On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > > 
> > > > For ICL, on Combo PHY the allowed max rates are:
> > > >  - HBR3 8.1 eDP (DDIA)
> > > >  - HBR2 5.4 DisplayPort (DDIB)
> > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > >  - DP on legacy connector - DDIC/D/E/F)
> > > > 
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > > 
> > > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 5109023abe28..3ee8e74cf2b8 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > > *intel_dp)
> > > >  	return 810000;
> > > >  }
> > > >  
> > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > +{
> > > > +	struct intel_digital_port *dig_port =
> > > > dp_to_dig_port(intel_dp);
> > > > +	enum port port = dig_port->base.port;
> > > > +
> > > > +	/* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > voltages
> > > > +	 * and on Combo PHY Port B the maximum supported is HBR2.
> > > > +	 */
> > > > +	if (port == PORT_B)
> > > > +		return 540000;
> > > > +
> > > > +	return 810000;
> > > > +}
> > > > +
> > > >  static void
> > > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > >  {
> > > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > *intel_dp)
> > > >  	/* This should only be done once */
> > > >  	WARN_ON(intel_dp->source_rates || intel_dp-
> > > > >num_source_rates);
> > > >  
> > > > -	if (IS_CANNONLAKE(dev_priv)) {
> > > > +	if (INTEL_GEN(dev_priv) >= 10) {
> > > >  		source_rates = cnl_rates;
> > > >  		size = ARRAY_SIZE(cnl_rates);
> > > > -		max_rate = cnl_max_source_rate(intel_dp);
> > > > +		if (IS_ICELAKE(dev_priv))
> > > > +			max_rate = icl_max_source_rate(intel_dp);
> > > > +		else
> > > > +			max_rate = cnl_max_source_rate(intel_dp);
> > 
> > Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> > any possible future platform would be using the ICL table instead of
> > the CNL one.
> 
> I agree... but I'd prefer s/IS_ICELAKE/gen >= 11

Ok, so remove IS_CANNONLAKE and only have the code for Gen >=11 right?
So remove the cnl_max_source_rate also?

Regards
Manasi

> 
> > 
> > 
> > > >  	} else if (IS_GEN9_LP(dev_priv)) {
> > > >  		source_rates = bxt_rates;
> > > >  		size = ARRAY_SIZE(bxt_rates);
> > > > -- 
> > > > 2.14.3
> > > > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Rodrigo Vivi June 15, 2018, 5:20 a.m. UTC | #6 
On Thu, Jun 14, 2018 at 05:45:03PM -0700, Manasi Navare wrote:
> On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > > From: Manasi Navare <manasi.d.navare@intel.com>
> > > > > 
> > > > > For ICL, on Combo PHY the allowed max rates are:
> > > > >  - HBR3 8.1 eDP (DDIA)
> > > > >  - HBR2 5.4 DisplayPort (DDIB)
> > > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > > >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > > >  - DP on legacy connector - DDIC/D/E/F)
> > > > > 
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > Cc: James Ausmus <james.ausmus@intel.com>
> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > > > 
> > > > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > > > 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > > >  1 file changed, 19 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 5109023abe28..3ee8e74cf2b8 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > > > *intel_dp)
> > > > >  	return 810000;
> > > > >  }
> > > > >  
> > > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > > +{
> > > > > +	struct intel_digital_port *dig_port =
> > > > > dp_to_dig_port(intel_dp);
> > > > > +	enum port port = dig_port->base.port;
> > > > > +
> > > > > +	/* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > > voltages
> > > > > +	 * and on Combo PHY Port B the maximum supported is HBR2.
> > > > > +	 */
> > > > > +	if (port == PORT_B)
> > > > > +		return 540000;
> > > > > +
> > > > > +	return 810000;
> > > > > +}
> > > > > +
> > > > >  static void
> > > > >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > >  {
> > > > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > > *intel_dp)
> > > > >  	/* This should only be done once */
> > > > >  	WARN_ON(intel_dp->source_rates || intel_dp-
> > > > > >num_source_rates);
> > > > >  
> > > > > -	if (IS_CANNONLAKE(dev_priv)) {
> > > > > +	if (INTEL_GEN(dev_priv) >= 10) {
> > > > >  		source_rates = cnl_rates;
> > > > >  		size = ARRAY_SIZE(cnl_rates);
> > > > > -		max_rate = cnl_max_source_rate(intel_dp);
> > > > > +		if (IS_ICELAKE(dev_priv))
> > > > > +			max_rate = icl_max_source_rate(intel_dp);
> > > > > +		else
> > > > > +			max_rate = cnl_max_source_rate(intel_dp);
> > > 
> > > Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> > > any possible future platform would be using the ICL table instead of
> > > the CNL one.
> > 
> > I agree... but I'd prefer s/IS_ICELAKE/gen >= 11
> 
> Ok, so remove IS_CANNONLAKE and only have the code for Gen >=11 right?
> So remove the cnl_max_source_rate also?

No no, the rest of the patch is okay and should stay...
only instead of IS_ICELAKE you use gen >= 11

> 
> Regards
> Manasi
> 
> > 
> > > 
> > > 
> > > > >  	} else if (IS_GEN9_LP(dev_priv)) {
> > > > >  		source_rates = bxt_rates;
> > > > >  		size = ARRAY_SIZE(bxt_rates);
> > > > > -- 
> > > > > 2.14.3
> > > > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Navare, Manasi June 19, 2018, 8:39 p.m. UTC | #7 
On Thu, Jun 14, 2018 at 12:23:36PM -0700, Rodrigo Vivi wrote:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare <manasi.d.navare@intel.com>
> > 
> > For ICL, on Combo PHY the allowed max rates are:
> >  - HBR3 8.1 eDP (DDIA)
> >  - HBR2 5.4 DisplayPort (DDIB)
> > and for MG PHY/TC DDI Ports allowed DP rates are:
> >  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> >  - DP on legacy connector - DDIC/D/E/F)
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> >  1 file changed, 19 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 5109023abe28..3ee8e74cf2b8 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> >  	return 810000;
> >  }
> >  
> > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +	enum port port = dig_port->base.port;
> > +
> > +	/* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> > +	 * and on Combo PHY Port B the maximum supported is HBR2.
> > +	 */
> > +	if (port == PORT_B)
> 
> A more generic way here would be COMBO and !eDP

Yes I can use the function intel_is_port_combophy() but I dont see that merged yet
Will have to wait to spin this patch in that case.


> 
> > +		return 540000;
> > +
> > +	return 810000;
> > +}
> > +
> >  static void
> >  intel_dp_set_source_rates(struct intel_dp *intel_dp)
> >  {
> > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> >  	/* This should only be done once */
> >  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> >  
> > -	if (IS_CANNONLAKE(dev_priv)) {
> > +	if (INTEL_GEN(dev_priv) >= 10) {
> >  		source_rates = cnl_rates;
> >  		size = ARRAY_SIZE(cnl_rates);
> > -		max_rate = cnl_max_source_rate(intel_dp);
> > +		if (IS_ICELAKE(dev_priv))
> 
> and gen >= 11
> 
> but changes can be in follow-up work, so

Yes will change that to use >= 11

Manasi

> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > +			max_rate = icl_max_source_rate(intel_dp);
> > +		else
> > +			max_rate = cnl_max_source_rate(intel_dp);
> >  	} else if (IS_GEN9_LP(dev_priv)) {
> >  		source_rates = bxt_rates;
> >  		size = ARRAY_SIZE(bxt_rates);
> > -- 
> > 2.14.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5109023abe28..3ee8e74cf2b8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -419,6 +419,20 @@  static int cnl_max_source_rate(struct intel_dp *intel_dp)
 	return 810000;
 }
 
+static int icl_max_source_rate(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum port port = dig_port->base.port;
+
+	/* On Combo PHY port A max speed is HBR3 for all Vccio voltages
+	 * and on Combo PHY Port B the maximum supported is HBR2.
+	 */
+	if (port == PORT_B)
+		return 540000;
+
+	return 810000;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -448,10 +462,13 @@  intel_dp_set_source_rates(struct intel_dp *intel_dp)
 	/* This should only be done once */
 	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 
-	if (IS_CANNONLAKE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 10) {
 		source_rates = cnl_rates;
 		size = ARRAY_SIZE(cnl_rates);
-		max_rate = cnl_max_source_rate(intel_dp);
+		if (IS_ICELAKE(dev_priv))
+			max_rate = icl_max_source_rate(intel_dp);
+		else
+			max_rate = cnl_max_source_rate(intel_dp);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);