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KVM: docs: mmu: KVM support exposing SLAT to guests

Message ID 1527358752-3943-1-git-send-email-liran.alon@oracle.com (mailing list archive)
State New, archived
Headers show

Commit Message

Liran Alon May 26, 2018, 6:19 p.m. UTC
Fix outdated statement that KVM is not able to expose SLAT
(Second-Layer-Address-Translation) to guests.
This was implemented a long time ago...

Signed-off-by: Liran Alon <liran.alon@oracle.com>
---
 Documentation/virtual/kvm/mmu.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Paolo Bonzini May 29, 2018, 5:07 p.m. UTC | #1
On 26/05/2018 20:19, Liran Alon wrote:
> Fix outdated statement that KVM is not able to expose SLAT
> (Second-Layer-Address-Translation) to guests.
> This was implemented a long time ago...
> 
> Signed-off-by: Liran Alon <liran.alon@oracle.com>
> ---
>  Documentation/virtual/kvm/mmu.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/virtual/kvm/mmu.txt b/Documentation/virtual/kvm/mmu.txt
> index 4a81bcc96bd6..e507a9e0421e 100644
> --- a/Documentation/virtual/kvm/mmu.txt
> +++ b/Documentation/virtual/kvm/mmu.txt
> @@ -49,8 +49,8 @@ The mmu supports first-generation mmu hardware, which allows an atomic switch
>  of the current paging mode and cr3 during guest entry, as well as
>  two-dimensional paging (AMD's NPT and Intel's EPT).  The emulated hardware
>  it exposes is the traditional 2/3/4 level x86 mmu, with support for global
> -pages, pae, pse, pse36, cr0.wp, and 1GB pages.  Work is in progress to support
> -exposing NPT capable hardware on NPT capable hosts.
> +pages, pae, pse, pse36, cr0.wp, and 1GB pages. Emulated hardware also
> +able to expose NPT capable hardware on NPT capable hosts.
>  
>  Translation
>  ===========
> 

Queued, thanks.

Paolo
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Patch

diff --git a/Documentation/virtual/kvm/mmu.txt b/Documentation/virtual/kvm/mmu.txt
index 4a81bcc96bd6..e507a9e0421e 100644
--- a/Documentation/virtual/kvm/mmu.txt
+++ b/Documentation/virtual/kvm/mmu.txt
@@ -49,8 +49,8 @@  The mmu supports first-generation mmu hardware, which allows an atomic switch
 of the current paging mode and cr3 during guest entry, as well as
 two-dimensional paging (AMD's NPT and Intel's EPT).  The emulated hardware
 it exposes is the traditional 2/3/4 level x86 mmu, with support for global
-pages, pae, pse, pse36, cr0.wp, and 1GB pages.  Work is in progress to support
-exposing NPT capable hardware on NPT capable hosts.
+pages, pae, pse, pse36, cr0.wp, and 1GB pages. Emulated hardware also
+able to expose NPT capable hardware on NPT capable hosts.
 
 Translation
 ===========