| Message ID | 20180524052341.12422-1-chris.packham@alliedtelesis.co.nz (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
Quoting Chris Packham (2018-05-23 22:23:41) > The correct fieldbit value for the NAND PLL reload trigger is 27. > > Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- Applied to clk-next -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 8491979f4096..68f05c53d40e 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { }; static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = { - { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */ + { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */ }; #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
The correct fieldbit value for the NAND PLL reload trigger is 27. Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- I can't remember where the value of 26 came from. Looking at the lsp source I have from Marvell it's always been 27, so I suspect I just messed up when porting. The only documentation I have is that register field is bits 21:27 without adding any detail as to which clock trees correspond to the individual bits so I'm not sure which clock tree was being triggered. drivers/clk/mvebu/clk-corediv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)