| Message ID | 20180608125602.17693-17-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Chris Wilson <chris@chris-wilson.co.uk> writes: > hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the > redundant specialism. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ------------------------ > 1 file changed, 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 60a8332a122e..25ad94b1b67e 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1697,28 +1697,6 @@ static inline u32 get_pd_offset(struct gen6_hw_ppgtt *ppgtt) > return ppgtt->base.pd.base.ggtt_offset << 10; > } > > -static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt, > - struct i915_request *rq) > -{ > - struct intel_engine_cs *engine = rq->engine; > - u32 *cs; > - > - /* NB: TLBs must be flushed and invalidated before a switch */ > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_LOAD_REGISTER_IMM(2); > - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); > - *cs++ = PP_DIR_DCLV_2G; > - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); > - *cs++ = get_pd_offset(ppgtt); > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt, > struct i915_request *rq) > { > @@ -2148,8 +2126,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) > ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; > if (intel_vgpu_active(i915) || IS_GEN6(i915)) > ppgtt->switch_mm = gen6_mm_switch; > - else if (IS_HASWELL(i915)) > - ppgtt->switch_mm = hsw_mm_switch; > else if (IS_GEN7(i915)) > ppgtt->switch_mm = gen7_mm_switch; > else > -- > 2.17.1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 60a8332a122e..25ad94b1b67e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1697,28 +1697,6 @@ static inline u32 get_pd_offset(struct gen6_hw_ppgtt *ppgtt) return ppgtt->base.pd.base.ggtt_offset << 10; } -static int hsw_mm_switch(struct gen6_hw_ppgtt *ppgtt, - struct i915_request *rq) -{ - struct intel_engine_cs *engine = rq->engine; - u32 *cs; - - /* NB: TLBs must be flushed and invalidated before a switch */ - cs = intel_ring_begin(rq, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_LOAD_REGISTER_IMM(2); - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); - *cs++ = PP_DIR_DCLV_2G; - *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); - *cs++ = get_pd_offset(ppgtt); - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - return 0; -} - static int gen7_mm_switch(struct gen6_hw_ppgtt *ppgtt, struct i915_request *rq) { @@ -2148,8 +2126,6 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915) ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; if (intel_vgpu_active(i915) || IS_GEN6(i915)) ppgtt->switch_mm = gen6_mm_switch; - else if (IS_HASWELL(i915)) - ppgtt->switch_mm = hsw_mm_switch; else if (IS_GEN7(i915)) ppgtt->switch_mm = gen7_mm_switch; else
hsw_mm_switch() and gen7_mm_switch() are identical, so let's remove the redundant specialism. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 24 ------------------------ 1 file changed, 24 deletions(-)