| Message ID | 20180522002558.29262-17-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 21, 2018 at 05:25:50PM -0700, Paulo Zanoni wrote: > From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > This patch enables hotplug interrupts for DP over TBT output on TC > ports. The TBT interrupts are enabled and handled irrespective of the > actual output type which could be DP Alternate, DP over TBT, native DP > or native HDMI. > > Cc: Animesh Manna <animesh.manna@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > --- > drivers/gpu/drm/i915/i915_irq.c | 49 ++++++++++++++++++++++++++++++----------- > drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++- > 2 files changed, 46 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 6b109991786f..9f1b01ca4ed1 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -115,11 +115,11 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { > [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC > }; > > -static const u32 hpd_tc_gen11[HPD_NUM_PINS] = { > - [HPD_PORT_C] = GEN11_TC1_HOTPLUG, > - [HPD_PORT_D] = GEN11_TC2_HOTPLUG, > - [HPD_PORT_E] = GEN11_TC3_HOTPLUG, > - [HPD_PORT_F] = GEN11_TC4_HOTPLUG > +static const u32 hpd_gen11[HPD_NUM_PINS] = { > + [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG, > + [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG, > + [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG, > + [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG > }; > > static const u32 hpd_icp[HPD_NUM_PINS] = { > @@ -2690,20 +2690,35 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, > static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) > { > u32 pin_mask = 0, long_mask = 0; > - u32 trigger_tc, dig_hotplug_reg; > + u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; > + u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; > > - trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; > if (trigger_tc) { > + u32 dig_hotplug_reg; > + > dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL); > I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); > > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, > - dig_hotplug_reg, hpd_tc_gen11, > + dig_hotplug_reg, hpd_gen11, > + gen11_port_hotplug_long_detect); > + } > + > + if (trigger_tbt) { > + u32 dig_hotplug_reg; > + > + dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL); > + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); > + > + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, > + dig_hotplug_reg, hpd_gen11, > gen11_port_hotplug_long_detect); > + } > + > + if (pin_mask) > intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); > - } else { > + else > DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir); > - } > } > > static irqreturn_t > @@ -3783,6 +3798,13 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) > GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | > GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); > I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); > + > + hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); > + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | > + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); > + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); > } > > static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) > @@ -3790,8 +3812,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) > u32 hotplug_irqs, enabled_irqs; > u32 val; > > - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11); > - hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK; > + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11); > + hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; > > val = I915_READ(GEN11_DE_HPD_IMR); > val &= ~hotplug_irqs; > @@ -4176,7 +4198,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > if (INTEL_GEN(dev_priv) >= 11) { > u32 de_hpd_masked = 0; > - u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK; > + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | > + GEN11_DE_TBT_HOTPLUG_MASK; > > GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); > gen11_hpd_detection_setup(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ce79913466a7..49a72320e794 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7059,7 +7059,16 @@ enum { > GEN11_TC3_HOTPLUG | \ > GEN11_TC2_HOTPLUG | \ > GEN11_TC1_HOTPLUG) > - > +#define GEN11_TBT4_HOTPLUG (1 << 3) > +#define GEN11_TBT3_HOTPLUG (1 << 2) > +#define GEN11_TBT2_HOTPLUG (1 << 1) > +#define GEN11_TBT1_HOTPLUG (1 << 0) > +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \ > + GEN11_TBT3_HOTPLUG | \ > + GEN11_TBT2_HOTPLUG | \ > + GEN11_TBT1_HOTPLUG) > + > +#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) > #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) > #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) > #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6b109991786f..9f1b01ca4ed1 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -115,11 +115,11 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC }; -static const u32 hpd_tc_gen11[HPD_NUM_PINS] = { - [HPD_PORT_C] = GEN11_TC1_HOTPLUG, - [HPD_PORT_D] = GEN11_TC2_HOTPLUG, - [HPD_PORT_E] = GEN11_TC3_HOTPLUG, - [HPD_PORT_F] = GEN11_TC4_HOTPLUG +static const u32 hpd_gen11[HPD_NUM_PINS] = { + [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG, + [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG, + [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG, + [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG }; static const u32 hpd_icp[HPD_NUM_PINS] = { @@ -2690,20 +2690,35 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) { u32 pin_mask = 0, long_mask = 0; - u32 trigger_tc, dig_hotplug_reg; + u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; + u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; - trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; if (trigger_tc) { + u32 dig_hotplug_reg; + dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL); I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, - dig_hotplug_reg, hpd_tc_gen11, + dig_hotplug_reg, hpd_gen11, + gen11_port_hotplug_long_detect); + } + + if (trigger_tbt) { + u32 dig_hotplug_reg; + + dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL); + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); + + intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, + dig_hotplug_reg, hpd_gen11, gen11_port_hotplug_long_detect); + } + + if (pin_mask) intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); - } else { + else DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir); - } } static irqreturn_t @@ -3783,6 +3798,13 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); + + hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); + hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); + I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) @@ -3790,8 +3812,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) u32 hotplug_irqs, enabled_irqs; u32 val; - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tc_gen11); - hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK; + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_gen11); + hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; val = I915_READ(GEN11_DE_HPD_IMR); val &= ~hotplug_irqs; @@ -4176,7 +4198,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 11) { u32 de_hpd_masked = 0; - u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK; + u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | + GEN11_DE_TBT_HOTPLUG_MASK; GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); gen11_hpd_detection_setup(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce79913466a7..49a72320e794 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7059,7 +7059,16 @@ enum { GEN11_TC3_HOTPLUG | \ GEN11_TC2_HOTPLUG | \ GEN11_TC1_HOTPLUG) - +#define GEN11_TBT4_HOTPLUG (1 << 3) +#define GEN11_TBT3_HOTPLUG (1 << 2) +#define GEN11_TBT2_HOTPLUG (1 << 1) +#define GEN11_TBT1_HOTPLUG (1 << 0) +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT4_HOTPLUG | \ + GEN11_TBT3_HOTPLUG | \ + GEN11_TBT2_HOTPLUG | \ + GEN11_TBT1_HOTPLUG) + +#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) #define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) #define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4)