| Message ID | 1527241772-48007-3-git-send-email-julien.thierry@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 25/05/18 11:48, Julien Thierry wrote: > > > On 25/05/18 11:41, Suzuki K Poulose wrote: >> On 25/05/18 11:39, Julien Thierry wrote: >>> >>> >>> On 25/05/18 11:36, Suzuki K Poulose wrote: >>>> On 25/05/18 11:17, Julien Thierry wrote: >>>>> >>>>> >>>>> On 25/05/18 11:04, Suzuki K Poulose wrote: >>>>>> On 25/05/18 10:49, Julien Thierry wrote: >>>>>>> Add a cpufeature indicating whether a cpu supports masking >>>>>>> interrupts >>>>>>> by priority. >>>>>> >>>>>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just >>>>>> the description ? >>>>> >>>>> More or less. >>>>> >>>>> It is just to have an easier condition in the rest of the series. >>>>> Basically the PRIO masking feature is enabled if we have a GICv3 >>>>> CPUIF working *and* the option was selected at build time. Before >>>>> this meant that I was checking for the GIC_CPUIF cap inside #ifdefs >>>>> (and putting alternatives depending on that inside #ifdefs as well). >>>>> >>>>> Having this as a separate feature feels easier to manage in the >>>>> code. It also makes it clearer at boot time that the kernel will be >>>>> using irq priorities (although I admit it was not the initial >>>>> intention): >>>>> >>>>> [ 0.000000] CPU features: detected: IRQ priority masking >>>>> >>>>> >>>>> But yes that new feature will be detected only if SYSREG_GIC_CPUIF >>>>> gets detected as well. >>>> >>>> Well, you could always wrap the check like : >>>> >>>> static inline bool system_has_irq_priority_masking(void) >>>> { >>>> return (IS_ENABLED(CONFIG_YOUR_CONFIG) && >>>> cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF)); >>>> } >>>> >>>> and use it everywhere. >>>> >>> >>> Yes, but I can't use that in the asm parts that use alternatives and >>> would need to surround them in #ifdef... :\ >> >> I thought there is _ALTERNATIVE_CFG() to base the alternative depend >> on a CONFIG_xxx ? >> Doesn't that solve the problem ? > > Right, I didn't see that one. It should work yes. > > I'll try that when working on the next version. I've been trying to use this now, but I can't figure out how. The _ALTERNATIVE_CFG does not seem to work in assembly code (despite having its own definition for __ASSEMBLY__), and the alternative_insn does not seem to be suited for instructions that take operands (or more than one operand) If I am mistaken, can you provide an example of how to use this in assembly with instructions having more than 1 operand? Cheers,
On 12/06/18 14:46, Julien Thierry wrote: > > > On 25/05/18 11:48, Julien Thierry wrote: >> >> >> On 25/05/18 11:41, Suzuki K Poulose wrote: >>> On 25/05/18 11:39, Julien Thierry wrote: >>>> >>>> >>>> On 25/05/18 11:36, Suzuki K Poulose wrote: >>>>> On 25/05/18 11:17, Julien Thierry wrote: >>>>>> >>>>>> >>>>>> On 25/05/18 11:04, Suzuki K Poulose wrote: >>>>>>> On 25/05/18 10:49, Julien Thierry wrote: >>>>>>>> Add a cpufeature indicating whether a cpu supports masking interrupts >>>>>>>> by priority. >>>>>>> >>>>>>> How is this different from the SYSREG_GIC_CPUIF cap ? Is it just >>>>>>> the description ? >>>>>> >>>>>> More or less. >>>>>> >>>>>> It is just to have an easier condition in the rest of the series. Basically the PRIO masking feature is enabled if we have a GICv3 CPUIF working *and* the option was selected at build time. Before this meant that I was checking for the GIC_CPUIF cap inside #ifdefs (and putting alternatives depending on that inside #ifdefs as well). >>>>>> >>>>>> Having this as a separate feature feels easier to manage in the code. It also makes it clearer at boot time that the kernel will be using irq priorities (although I admit it was not the initial intention): >>>>>> >>>>>> [ 0.000000] CPU features: detected: IRQ priority masking >>>>>> >>>>>> >>>>>> But yes that new feature will be detected only if SYSREG_GIC_CPUIF gets detected as well. >>>>> >>>>> Well, you could always wrap the check like : >>>>> >>>>> static inline bool system_has_irq_priority_masking(void) >>>>> { >>>>> return (IS_ENABLED(CONFIG_YOUR_CONFIG) && cpus_have_const_cap(HWCAP_SYSREG_GIC_CPUIF)); >>>>> } >>>>> >>>>> and use it everywhere. >>>>> >>>> >>>> Yes, but I can't use that in the asm parts that use alternatives and would need to surround them in #ifdef... :\ >>> >>> I thought there is _ALTERNATIVE_CFG() to base the alternative depend on a CONFIG_xxx ? >>> Doesn't that solve the problem ? >> >> Right, I didn't see that one. It should work yes. >> >> I'll try that when working on the next version. > > I've been trying to use this now, but I can't figure out how. > > The _ALTERNATIVE_CFG does not seem to work in assembly code (despite having its own definition for __ASSEMBLY__), and the alternative_insn does not seem to be suited for instructions that take operands (or more than one operand) > > If I am mistaken, can you provide an example of how to use this in assembly with instructions having more than 1 operand? I am sorry, but I think the ALTERNATIVE_CFG is not the right one, as it omits the entire block, if the CONFIG is not enabled. So you are left with only three choices : 1) Use alternative call back 2) Stick to two separate caps. 3) Use #ifdef Cheers Suzuki
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index bc51b72..cd8f9ed 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -48,7 +48,8 @@ #define ARM64_HAS_CACHE_IDC 27 #define ARM64_HAS_CACHE_DIC 28 #define ARM64_HW_DBM 29 +#define ARM64_HAS_IRQ_PRIO_MASKING 30 -#define ARM64_NCAPS 30 +#define ARM64_NCAPS 31 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e03e897..a177104 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1202,6 +1202,21 @@ static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) .cpu_enable = cpu_enable_hw_dbm, }, #endif +#ifdef CONFIG_USE_ICC_SYSREGS_FOR_IRQFLAGS + { + /* + * Depends on having GICv3 + */ + .desc = "IRQ priority masking", + .capability = ARM64_HAS_IRQ_PRIO_MASKING, + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .matches = has_useable_gicv3_cpuif, + .sys_reg = SYS_ID_AA64PFR0_EL1, + .field_pos = ID_AA64PFR0_GIC_SHIFT, + .sign = FTR_UNSIGNED, + .min_field_value = 1, + }, +#endif {}, };
Add a cpufeature indicating whether a cpu supports masking interrupts by priority. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> --- arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/kernel/cpufeature.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-)