| Message ID | 1529594036-25036-1-git-send-email-vandita.kulkarni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > Alpha blending with alpha 0 and 0xff passes through > alpha math and rounding logic causing differences > compared to fully transparent or opaque plane,resulting > in CRC mismatch. > This WA on icl and above enables hardware to bypass alpha > math and rounding for per pixel alpha values of 00 and 0xff > > v2: Fix patchwork checkpatch warnings. > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4bfd7a9..b66ec9b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7366,6 +7366,14 @@ enum { > #define BDW_SCRATCH1 _MMIO(0xb11c) > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > +/*GEN11 chicken */ > +#define _PIPEA_CHICKEN 0x70038 > +#define _PIPEB_CHICKEN 0x71038 > +#define _PIPEC_CHICKEN 0x72038 > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ > + _PIPEB_CHICKEN) > + > /* PCH */ > > /* south display engine interrupt: IBX */ > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 2c8fef3..3d849ec 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > struct intel_atomic_state *old_intel_state = > to_intel_atomic_state(old_state); > bool psl_clkgate_wa; > + u32 pipe_chicken; > > if (WARN_ON(intel_crtc->active)) > return; > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, > */ > intel_color_load_luts(&pipe_config->base); > > + /* > + * Display WA #1153: enable hardware to bypass the alpha math > + * and rounding for per-pixel values 00 and 0xff > + */ > + if (INTEL_GEN(dev_priv) >= 11) { > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > + pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); > + } This would enable the wa by default for gen > 11. Would this impact for non 00, 0xff alpha cases? In other words, should we enable the wa only when alpha is 00/0xff and not enable for other values? Thanks, Radhakrishna(RK) Sripada > + > intel_ddi_set_pipe_settings(pipe_config); > if (!transcoder_is_dsi(cpu_transcoder)) > intel_ddi_enable_transcoder_func(pipe_config); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> -----Original Message----- > From: Sripada, Radhakrishna > Sent: Friday, June 22, 2018 2:39 AM > To: Kulkarni, Vandita <vandita.kulkarni@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten > <maarten.lankhorst@intel.com> > Subject: Re: [Intel-gfx] [v2] drm/i915: Enable hw workaround to bypass > alpha > > On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through alpha math and > > rounding logic causing differences compared to fully transparent or > > opaque plane,resulting in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha math and > > rounding for per pixel alpha values of 00 and 0xff > > > > v2: Fix patchwork checkpatch warnings. > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..b66ec9b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 > _MMIO(0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << > 2) > > > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > > > /* south display engine interrupt: IBX */ diff --git > > a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..3d849ec 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state = > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > + if (INTEL_GEN(dev_priv) >= 11) { > > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > PER_PIXEL_ALPHA_BYPASS_EN); > > + } > This would enable the wa by default for gen > 11. Would this impact for non > 00, 0xff alpha cases? No Impact on non 0xff or 00 cases. Verified on icl. > In other words, should we enable the wa only when alpha is 00/0xff and not > enable for other values? No it can remain set. > > Thanks, > Radhakrishna(RK) Sripada > > + > > intel_ddi_set_pipe_settings(pipe_config); > > if (!transcoder_is_dsi(cpu_transcoder)) > > intel_ddi_enable_transcoder_func(pipe_config); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
tor 2018-06-21 klockan 14:09 -0700 skrev Radhakrishna Sripada: > On Thu, Jun 21, 2018 at 08:43:56PM +0530, Vandita Kulkarni wrote: > > Alpha blending with alpha 0 and 0xff passes through > > alpha math and rounding logic causing differences > > compared to fully transparent or opaque plane,resulting > > in CRC mismatch. > > This WA on icl and above enables hardware to bypass alpha > > math and rounding for per pixel alpha values of 00 and 0xff > > > > v2: Fix patchwork checkpatch warnings. > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 2 files changed, 20 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 4bfd7a9..b66ec9b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7366,6 +7366,14 @@ enum { > > #define BDW_SCRATCH1 _MMIO( > > 0xb11c) > > #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) > > > > +/*GEN11 chicken */ > > +#define _PIPEA_CHICKEN 0x70038 > > +#define _PIPEB_CHICKEN 0x71038 > > +#define _PIPEC_CHICKEN 0x72038 > > +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) > > +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, > > _PIPEA_CHICKEN,\ > > + _PIPEB_CHICKEN) > > + > > /* PCH */ > > > > /* south display engine interrupt: IBX */ > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 2c8fef3..3d849ec 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > struct intel_atomic_state *old_intel_state = > > to_intel_atomic_state(old_state); > > bool psl_clkgate_wa; > > + u32 pipe_chicken; > > > > if (WARN_ON(intel_crtc->active)) > > return; > > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct > > intel_crtc_state *pipe_config, > > */ > > intel_color_load_luts(&pipe_config->base); > > > > + /* > > + * Display WA #1153: enable hardware to bypass the alpha > > math > > + * and rounding for per-pixel values 00 and 0xff > > + */ > > + if (INTEL_GEN(dev_priv) >= 11) { > > + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); > > + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) > > + I915_WRITE_FW(PIPE_CHICKEN(pipe), > > + pipe_chicken | > > PER_PIXEL_ALPHA_BYPASS_EN); > > + } > > This would enable the wa by default for gen > 11. Would this impact > for non 00, 0xff alpha cases? > In other words, should we enable the wa only when alpha is 00/0xff > and not enable for other values? > This is about per pixel values, unlike the plane alpha. This looks at the pixel contents, so if a pixel has (0xff, R, G, B), we pass through RGB unmodified. If it's (0x00, R, G, B), we do the same for the background pixel without introducing rounding errors. When we program plane alpha, we handle 0x00 by disabling the plane, and 0xff by disabling plane alpha and making the plane opaque. Thanks for the patch, pushed. :) ~Maarten
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..b66ec9b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7366,6 +7366,14 @@ enum { #define BDW_SCRATCH1 _MMIO(0xb11c) #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) +/*GEN11 chicken */ +#define _PIPEA_CHICKEN 0x70038 +#define _PIPEB_CHICKEN 0x71038 +#define _PIPEC_CHICKEN 0x72038 +#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) +#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ + _PIPEB_CHICKEN) + /* PCH */ /* south display engine interrupt: IBX */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2c8fef3..3d849ec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, struct intel_atomic_state *old_intel_state = to_intel_atomic_state(old_state); bool psl_clkgate_wa; + u32 pipe_chicken; if (WARN_ON(intel_crtc->active)) return; @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, */ intel_color_load_luts(&pipe_config->base); + /* + * Display WA #1153: enable hardware to bypass the alpha math + * and rounding for per-pixel values 00 and 0xff + */ + if (INTEL_GEN(dev_priv) >= 11) { + pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); + if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) + I915_WRITE_FW(PIPE_CHICKEN(pipe), + pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN); + } + intel_ddi_set_pipe_settings(pipe_config); if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_enable_transcoder_func(pipe_config);
Alpha blending with alpha 0 and 0xff passes through alpha math and rounding logic causing differences compared to fully transparent or opaque plane,resulting in CRC mismatch. This WA on icl and above enables hardware to bypass alpha math and rounding for per pixel alpha values of 00 and 0xff v2: Fix patchwork checkpatch warnings. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ 2 files changed, 20 insertions(+)