| Message ID | 20180622010322.92851-1-tarun.vyas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 2018-06-21 at 18:03 -0700, Tarun Vyas wrote: > This is a lockless version of the exisiting psr_wait_for_idle(). > We want to wait for PSR to idle out inside intel_pipe_update_start. > At the time of a pipe update, we should never race with any psr > enable or disable code, which is a part of crtc enable/disable. So, > we can live w/o taking any psr locks at all. > The follow up patch will use this lockless wait inside pipe_update_ > start to wait for PSR to idle out before checking for vblank evasion. > > Even if psr is never enabled, psr2_enabled will be false and this > function will wait for PSR1 to idle out, which should just return > immediately, so a very short (~1-2 usec) wait for cases where PSR > is disabled. > > Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> > --- > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_psr.c | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 578346b8d7e2..a48aad0f99bf 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1920,6 +1920,7 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > struct intel_crtc_state *crtc_state); > void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool > debug); > void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 > psr_iir); > +void psr_wait_for_idle_lockless(struct drm_i915_private *dev_priv); > > /* intel_runtime_pm.c */ > int intel_power_domains_init(struct drm_i915_private *); > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index aea81ace854b..425147444f69 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -757,6 +757,25 @@ void intel_psr_disable(struct intel_dp > *intel_dp, > cancel_work_sync(&dev_priv->psr.work); > } > > +void psr_wait_for_idle_lockless(struct drm_i915_private *dev_priv) > +{ > + i915_reg_t reg; > + u32 mask; > + int err; > + > + if (dev_priv->psr.psr2_enabled) { > + reg = EDP_PSR2_STATUS; > + mask = EDP_PSR2_STATUS_STATE_MASK; > + } else { > + reg = EDP_PSR_STATUS; > + mask = EDP_PSR_STATUS_STATE_MASK; > + } > + > + err = intel_wait_for_register(dev_priv, reg, mask, > EDP_PSR_STATUS_STATE_IDLE, 25); A comment explaining the rationale for 25 ms is necessary here. > + if (err) > + DRM_ERROR("Timed out waiting for PSR Idle for pipe > update\n"); > +} > + > static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) > { > struct intel_dp *intel_dp;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 578346b8d7e2..a48aad0f99bf 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1920,6 +1920,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug); void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir); +void psr_wait_for_idle_lockless(struct drm_i915_private *dev_priv); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index aea81ace854b..425147444f69 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -757,6 +757,25 @@ void intel_psr_disable(struct intel_dp *intel_dp, cancel_work_sync(&dev_priv->psr.work); } +void psr_wait_for_idle_lockless(struct drm_i915_private *dev_priv) +{ + i915_reg_t reg; + u32 mask; + int err; + + if (dev_priv->psr.psr2_enabled) { + reg = EDP_PSR2_STATUS; + mask = EDP_PSR2_STATUS_STATE_MASK; + } else { + reg = EDP_PSR_STATUS; + mask = EDP_PSR_STATUS_STATE_MASK; + } + + err = intel_wait_for_register(dev_priv, reg, mask, EDP_PSR_STATUS_STATE_IDLE, 25); + if (err) + DRM_ERROR("Timed out waiting for PSR Idle for pipe update\n"); +} + static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) { struct intel_dp *intel_dp;
This is a lockless version of the exisiting psr_wait_for_idle(). We want to wait for PSR to idle out inside intel_pipe_update_start. At the time of a pipe update, we should never race with any psr enable or disable code, which is a part of crtc enable/disable. So, we can live w/o taking any psr locks at all. The follow up patch will use this lockless wait inside pipe_update_ start to wait for PSR to idle out before checking for vblank evasion. Even if psr is never enabled, psr2_enabled will be false and this function will wait for PSR1 to idle out, which should just return immediately, so a very short (~1-2 usec) wait for cases where PSR is disabled. Signed-off-by: Tarun Vyas <tarun.vyas@intel.com> --- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+)