diff mbox

[v3,1/2] drm/i915: Lockless wait for PSR idle.

Message ID 20180622085108.2917-1-tarun.vyas@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tarun Vyas June 22, 2018, 8:51 a.m. UTC
Before checking for vblank evasion in pipe_update_start, we
need to wait for PSR idle. intel_psr.c already has psr_wait_for_idle
but we don't need any psr locks in pipe_update_start anyway b/c
psr_enable/disable won't race there. There is some code duplication
here but can't help it (borrowed from psr_wait_for_idle).

Signed-off-by: Tarun Vyas <tarun.vyas@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

Comments

Tarun Vyas June 22, 2018, 8:55 a.m. UTC | #1
On Fri, Jun 22, 2018 at 01:51:08AM -0700, Tarun Vyas wrote:
> Before checking for vblank evasion in pipe_update_start, we
> need to wait for PSR idle. intel_psr.c already has psr_wait_for_idle
> but we don't need any psr locks in pipe_update_start anyway b/c
> psr_enable/disable won't race there. There is some code duplication
> here but can't help it (borrowed from psr_wait_for_idle).
> 
> Signed-off-by: Tarun Vyas <tarun.vyas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d7dbca1aabff..935eb3d5d9bb 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1919,6 +1919,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state);
>  void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
>  void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
> +void intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
>  
>  /* intel_runtime_pm.c */
>  int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..75e2035ba29f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -883,6 +883,23 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>  	cancel_delayed_work_sync(&dev_priv->psr.work);
>  }
>  
> +void intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
> +{
> +	i915_reg_t reg;
> +	u32 mask;
> +
> +	if (dev_priv->psr.psr2_enabled) {
> +		reg = EDP_PSR2_STATUS;
> +		mask = EDP_PSR2_STATUS_STATE_MASK;
> +	} else {
> +		reg = EDP_PSR_STATUS;
> +		mask = EDP_PSR_STATUS_STATE_MASK;
> +	}
> +
> +	if (intel_wait_for_register(dev_priv, reg, mask, 0, 25))
> +		DRM_ERROR("Timed out waiting for PSR Idle\n");
> +}
> +
>  static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_dp *intel_dp;

Wrong patch. Please ignore.
> -- 
> 2.13.5
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d7dbca1aabff..935eb3d5d9bb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1919,6 +1919,7 @@  void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state);
 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
+void intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
 
 /* intel_runtime_pm.c */
 int intel_power_domains_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1de..75e2035ba29f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -883,6 +883,23 @@  void intel_psr_disable(struct intel_dp *intel_dp,
 	cancel_delayed_work_sync(&dev_priv->psr.work);
 }
 
+void intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
+{
+	i915_reg_t reg;
+	u32 mask;
+
+	if (dev_priv->psr.psr2_enabled) {
+		reg = EDP_PSR2_STATUS;
+		mask = EDP_PSR2_STATUS_STATE_MASK;
+	} else {
+		reg = EDP_PSR_STATUS;
+		mask = EDP_PSR_STATUS_STATE_MASK;
+	}
+
+	if (intel_wait_for_register(dev_priv, reg, mask, 0, 25))
+		DRM_ERROR("Timed out waiting for PSR Idle\n");
+}
+
 static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
 {
 	struct intel_dp *intel_dp;