| Message ID | 20180625120304.7543-17-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@siol.net> wrote: > Current DW HDMI PHY code never prepares and enables PHY clock after it is > created. It's just used as it is. This may work in some cases, but it's > clearly wrong. Fix it by adding proper calls to enable/disable PHY > clock. > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> So why does it work on the H3? Because there's only one PLL that the whole display pipeline uses? We should probably tag this for stable. So, Cc: <stable@vger.kernel.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@siol.net> wrote: > > Current DW HDMI PHY code never prepares and enables PHY clock after it is > > created. It's just used as it is. This may work in some cases, but it's > > clearly wrong. Fix it by adding proper calls to enable/disable PHY > > clock. > > > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > So why does it work on the H3? Because there's only one PLL that the whole > display pipeline uses? Yes, there is only one PLL_VIDEO and TCON and HDMI controller already enabled it. Best regards, Jernej > > We should probably tag this for stable. So, > > Cc: <stable@vger.kernel.org> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a): > On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@siol.net> wrote: > > Current DW HDMI PHY code never prepares and enables PHY clock after it is > > created. It's just used as it is. This may work in some cases, but it's > > clearly wrong. Fix it by adding proper calls to enable/disable PHY > > clock. > > > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > So why does it work on the H3? Because there's only one PLL that the whole > display pipeline uses? > > We should probably tag this for stable. So, > > Cc: <stable@vger.kernel.org> > Reviewed-by: Chen-Yu Tsai <wens@csie.org> Same question as before, how this should be handled? Can I send separate patch with same content to stable ML only? Best regards, Jernej
On Sat, Jun 30, 2018 at 3:19 AM, Jernej Škrabec <jernej.skrabec@siol.net> wrote: > Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a): >> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@siol.net> > wrote: >> > Current DW HDMI PHY code never prepares and enables PHY clock after it is >> > created. It's just used as it is. This may work in some cases, but it's >> > clearly wrong. Fix it by adding proper calls to enable/disable PHY >> > clock. >> > >> > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") >> > >> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> >> >> So why does it work on the H3? Because there's only one PLL that the whole >> display pipeline uses? >> >> We should probably tag this for stable. So, >> >> Cc: <stable@vger.kernel.org> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > Same question as before, how this should be handled? Can I send separate patch > with same content to stable ML only? Yes, including the hash of the commit which is already in Linus' tree. So you have to send it after the next -rc1. ChenYu
diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 5a52fc489a9d..966688f04741 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c @@ -477,13 +477,15 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) dev_err(dev, "Couldn't create the PHY clock\n"); goto err_put_clk_pll0; } + + clk_prepare_enable(phy->clk_phy); } phy->rst_phy = of_reset_control_get_shared(node, "phy"); if (IS_ERR(phy->rst_phy)) { dev_err(dev, "Could not get phy reset control\n"); ret = PTR_ERR(phy->rst_phy); - goto err_put_clk_pll0; + goto err_disable_clk_phy; } ret = reset_control_deassert(phy->rst_phy); @@ -514,6 +516,8 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) reset_control_assert(phy->rst_phy); err_put_rst_phy: reset_control_put(phy->rst_phy); +err_disable_clk_phy: + clk_disable_unprepare(phy->clk_phy); err_put_clk_pll0: if (phy->variant->has_phy_clk) clk_put(phy->clk_pll0); @@ -531,6 +535,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) clk_disable_unprepare(phy->clk_mod); clk_disable_unprepare(phy->clk_bus); + clk_disable_unprepare(phy->clk_phy); reset_control_assert(phy->rst_phy);
Current DW HDMI PHY code never prepares and enables PHY clock after it is created. It's just used as it is. This may work in some cases, but it's clearly wrong. Fix it by adding proper calls to enable/disable PHY clock. Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)