| Message ID | 20180705153230.32656-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Jul 05, 2018 at 04:32:30PM +0100, Chris Wilson wrote: > There's no magic bit0 for gen3, it's the same dword length parameter as > elsewhere and needs to be zero. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/selftests/i915_request.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c > index 675017bf59dd..cc27edc40356 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_request.c > +++ b/drivers/gpu/drm/i915/selftests/i915_request.c > @@ -594,11 +594,8 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915) > } else if (gen >= 6) { > *cmd++ = MI_BATCH_BUFFER_START | 1 << 8; > *cmd++ = lower_32_bits(vma->node.start); > - } else if (gen >= 4) { > - *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > - *cmd++ = lower_32_bits(vma->node.start); > } else { > - *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | 1; > + *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > *cmd++ = lower_32_bits(vma->node.start); > } > *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */ > -- > 2.18.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 675017bf59dd..cc27edc40356 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -594,11 +594,8 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915) } else if (gen >= 6) { *cmd++ = MI_BATCH_BUFFER_START | 1 << 8; *cmd++ = lower_32_bits(vma->node.start); - } else if (gen >= 4) { - *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; - *cmd++ = lower_32_bits(vma->node.start); } else { - *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | 1; + *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; *cmd++ = lower_32_bits(vma->node.start); } *cmd++ = MI_BATCH_BUFFER_END; /* terminate early in case of error */
There's no magic bit0 for gen3, it's the same dword length parameter as elsewhere and needs to be zero. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/selftests/i915_request.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)