| Message ID | 20180706115402.18547-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 6 July 2018 at 12:54, Chris Wilson <chris@chris-wilson.co.uk> wrote: > If we have just completed a WC write, we must ensure that the WCB (Write > Combining Buffer) is flushed out to main memory before we can expect to > see the results. This is especially important when mixing WC with GTT as > the physical paths are different and cachelines are not naturally flushed. > > Testcase: igt/drv_selftests/live_coherency #gdg > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
On 06/07/2018 12:54, Chris Wilson wrote: > If we have just completed a WC write, we must ensure that the WCB (Write > Combining Buffer) is flushed out to main memory before we can expect to > see the results. This is especially important when mixing WC with GTT as > the physical paths are different and cachelines are not naturally flushed. > > Testcase: igt/drv_selftests/live_coherency #gdg > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 0c0a1a959d0b..be63e8bbb6d2 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -837,6 +837,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) > } > break; > > + case I915_GEM_DOMAIN_WC: > + wmb(); > + break; > + > case I915_GEM_DOMAIN_CPU: > i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); > break; > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko
On Fri, Jul 06, 2018 at 12:54:02PM +0100, Chris Wilson wrote: > If we have just completed a WC write, we must ensure that the WCB (Write > Combining Buffer) is flushed out to main memory before we can expect to > see the results. This is especially important when mixing WC with GTT as > the physical paths are different and cachelines are not naturally flushed. > > Testcase: igt/drv_selftests/live_coherency #gdg > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 0c0a1a959d0b..be63e8bbb6d2 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -837,6 +837,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) > } > break; > > + case I915_GEM_DOMAIN_WC: > + wmb(); > + break; > + > case I915_GEM_DOMAIN_CPU: > i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); > break; > -- > 2.18.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0c0a1a959d0b..be63e8bbb6d2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -837,6 +837,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) } break; + case I915_GEM_DOMAIN_WC: + wmb(); + break; + case I915_GEM_DOMAIN_CPU: i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); break;
If we have just completed a WC write, we must ensure that the WCB (Write Combining Buffer) is flushed out to main memory before we can expect to see the results. This is especially important when mixing WC with GTT as the physical paths are different and cachelines are not naturally flushed. Testcase: igt/drv_selftests/live_coherency #gdg Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ 1 file changed, 4 insertions(+)