| Message ID | 20180706142323.25699-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 06, 2018 at 03:23:22PM +0100, Chris Wilson wrote: > Replace the magic bit with the proper symbolic name for instructing > MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT > address (still virtual!) on gen4+. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++-- > drivers/gpu/drm/i915/selftests/i915_gem_coherency.c | 4 ++-- > drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 ++-- > drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +- > 4 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c > index 1193dd36913a..ab662dabcff7 100644 > --- a/drivers/gpu/drm/i915/selftests/huge_pages.c > +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c > @@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) > *cmd++ = val; > } else if (gen >= 4) { > *cmd++ = MI_STORE_DWORD_IMM_GEN4 | > - (gen < 6 ? 1 << 22 : 0); > + (gen < 6 ? MI_USE_GGTT : 0); > *cmd++ = 0; > *cmd++ = offset; > *cmd++ = val; > } else { > - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22; > + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > *cmd++ = offset; > *cmd++ = val; > } > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > index cb9eef1635e1..294c58aba2c1 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, > *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); > *cs++ = v; Missed the gen8+ case here? > } else if (INTEL_GEN(i915) >= 4) { > - *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; > + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; So here we use ggtt on all gens. In the other tests we use ppgtt on gen6+. Ah, this one uses the kernel context apparently. I guess that's the reason? > *cs++ = 0; > *cs++ = i915_ggtt_offset(vma) + offset; > *cs++ = v; > } else { > - *cs++ = MI_STORE_DWORD_IMM | 1 << 22; > + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > *cs++ = i915_ggtt_offset(vma) + offset; > *cs++ = v; > *cs++ = MI_NOOP; > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > index 0d8e719802fa..65100d3e31cf 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > @@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) > *cmd++ = value; > } else if (gen >= 4) { > *cmd++ = MI_STORE_DWORD_IMM_GEN4 | > - (gen < 6 ? 1 << 22 : 0); > + (gen < 6 ? MI_USE_GGTT : 0); > *cmd++ = 0; > *cmd++ = offset; > *cmd++ = value; > } else { > - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22; > + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > *cmd++ = offset; > *cmd++ = value; > } > diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > index 5cb808dc5b50..0fc6da81f86e 100644 > --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > @@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h, > *batch++ = MI_BATCH_BUFFER_START | 1 << 8; > *batch++ = lower_32_bits(vma->node.start); > } else if (INTEL_GEN(i915) >= 4) { > - *batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; > + *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *batch++ = 0; > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = rq->fence.seqno; > -- > 2.18.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Ville Syrjälä (2018-07-06 15:47:25) > On Fri, Jul 06, 2018 at 03:23:22PM +0100, Chris Wilson wrote: > > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > > index cb9eef1635e1..294c58aba2c1 100644 > > --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c > > @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, > > *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); > > *cs++ = v; > > Missed the gen8+ case here? > > > } else if (INTEL_GEN(i915) >= 4) { > > - *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; > > + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > > So here we use ggtt on all gens. In the other tests we use ppgtt on > gen6+. Ah, this one uses the kernel context apparently. I guess that's > the reason? If memory serves, yes, this was deliberately trying to use the ppGTT in this case. I guess I need to check this against the full-ppgtt patches for gen7 (although shard-hsw didn't flag anything iirc), but this should probably have a (gen < 6 ? MI_USE_GGTT : 0) here. -Chris
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 1193dd36913a..ab662dabcff7 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) *cmd++ = val; } else if (gen >= 4) { *cmd++ = MI_STORE_DWORD_IMM_GEN4 | - (gen < 6 ? 1 << 22 : 0); + (gen < 6 ? MI_USE_GGTT : 0); *cmd++ = 0; *cmd++ = offset; *cmd++ = val; } else { - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22; + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; *cmd++ = offset; *cmd++ = val; } diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c index cb9eef1635e1..294c58aba2c1 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = v; } else if (INTEL_GEN(i915) >= 4) { - *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = 0; *cs++ = i915_ggtt_offset(vma) + offset; *cs++ = v; } else { - *cs++ = MI_STORE_DWORD_IMM | 1 << 22; + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; *cs++ = i915_ggtt_offset(vma) + offset; *cs++ = v; *cs++ = MI_NOOP; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 0d8e719802fa..65100d3e31cf 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) *cmd++ = value; } else if (gen >= 4) { *cmd++ = MI_STORE_DWORD_IMM_GEN4 | - (gen < 6 ? 1 << 22 : 0); + (gen < 6 ? MI_USE_GGTT : 0); *cmd++ = 0; *cmd++ = offset; *cmd++ = value; } else { - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22; + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; *cmd++ = offset; *cmd++ = value; } diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 5cb808dc5b50..0fc6da81f86e 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h, *batch++ = MI_BATCH_BUFFER_START | 1 << 8; *batch++ = lower_32_bits(vma->node.start); } else if (INTEL_GEN(i915) >= 4) { - *batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; + *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno;
Replace the magic bit with the proper symbolic name for instructing MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT address (still virtual!) on gen4+. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++-- drivers/gpu/drm/i915/selftests/i915_gem_coherency.c | 4 ++-- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 ++-- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-)