diff mbox

[1/3] clk: tegra: refactor 7.1 div calculation

Message ID 1530617721-5767-1-git-send-email-avienamo@nvidia.com (mailing list archive)
State Changes Requested, archived
Headers show

Commit Message

Aapo Vienamo July 3, 2018, 11:35 a.m. UTC 
From: Peter De Schrijver <pdeschrijver@nvidia.com>

Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.

Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
---
 drivers/clk/tegra/Makefile      |  1 +
 drivers/clk/tegra/clk-divider.c | 30 ++++--------------------
 drivers/clk/tegra/clk.h         |  3 +++
 drivers/clk/tegra/div71.c       | 51 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 60 insertions(+), 25 deletions(-)
 create mode 100644 drivers/clk/tegra/div71.c

Comments

Peter Geis July 3, 2018, 3:10 p.m. UTC | #1 
Good Morning,

Just a heads up.
During compilation with your patches, I get the following warning:

In file included from ./arch/arm/include/asm/div64.h:127:0,
                  from ./include/linux/kernel.h:174,
                  from drivers/clk/tegra/div71.c:17:
drivers/clk/tegra/div71.c: In function ‘div71_get’:
./include/asm-generic/div64.h:222:28: warning: comparison of distinct 
pointer types lacks a cast
   (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
                             ^
drivers/clk/tegra/div71.c:40:2: note: in expansion of macro ‘do_div’
   do_div(divider_ux1, rate);
   ^~~~~~

Very Respectfully,
Peter Geis


On 07/03/2018 07:35 AM, Aapo Vienamo wrote:
> From: Peter De Schrijver <pdeschrijver@nvidia.com>
> 
> Move this to a separate file so it can be used to calculate the sdmmc
> clock dividers.
> 
> Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
> ---
>   drivers/clk/tegra/Makefile      |  1 +
>   drivers/clk/tegra/clk-divider.c | 30 ++++--------------------
>   drivers/clk/tegra/clk.h         |  3 +++
>   drivers/clk/tegra/div71.c       | 51 +++++++++++++++++++++++++++++++++++++++++
>   4 files changed, 60 insertions(+), 25 deletions(-)
>   create mode 100644 drivers/clk/tegra/div71.c
> 
> diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
> index b716923..6d4f563 100644
> --- a/drivers/clk/tegra/Makefile
> +++ b/drivers/clk/tegra/Makefile
> @@ -24,3 +24,4 @@ obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
>   obj-y					+= cvb.o
>   obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
>   obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
> +obj-y					+= div71.o
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index 16e0aee..ad87858 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -32,35 +32,15 @@
>   static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
>   		   unsigned long parent_rate)
>   {
> -	u64 divider_ux1 = parent_rate;
> -	u8 flags = divider->flags;
> -	int mul;
> -
> -	if (!rate)
> -		return 0;
> -
> -	mul = get_mul(divider);
> -
> -	if (!(flags & TEGRA_DIVIDER_INT))
> -		divider_ux1 *= mul;
> -
> -	if (flags & TEGRA_DIVIDER_ROUND_UP)
> -		divider_ux1 += rate - 1;
> -
> -	do_div(divider_ux1, rate);
> -
> -	if (flags & TEGRA_DIVIDER_INT)
> -		divider_ux1 *= mul;
> +	int div;
>   
> -	divider_ux1 -= mul;
> +	div = div71_get(rate, parent_rate, divider->width, divider->frac_width,
> +			divider->flags);
>   
> -	if ((s64)divider_ux1 < 0)
> +	if (div < 0)
>   		return 0;
>   
> -	if (divider_ux1 > get_max_div(divider))
> -		return get_max_div(divider);
> -
> -	return divider_ux1;
> +	return div;
>   }
>   
>   static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index e1f8846..f14e136 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -811,6 +811,9 @@ extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
>   int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
>   u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
>   int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> +	      u8 frac_width, u8 flags);
> +
>   
>   /* Combined read fence with delay */
>   #define fence_udelay(delay, reg)	\
> diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c
> new file mode 100644
> index 0000000..27b3846
> --- /dev/null
> +++ b/drivers/clk/tegra/div71.c
> @@ -0,0 +1,51 @@
> +/*
> + * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/kernel.h>
> +
> +#include "clk.h"
> +
> +#define div_mask(w) ((1 << (w)) - 1)
> +
> +int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
> +	      u8 frac_width, u8 flags)
> +{
> +	s64 divider_ux1 = parent_rate;
> +	int mul;
> +
> +	if (!rate)
> +		return 0;
> +
> +	mul = 1 << frac_width;
> +
> +	if (!(flags & TEGRA_DIVIDER_INT))
> +		divider_ux1 *= mul;
> +
> +	if (flags & TEGRA_DIVIDER_ROUND_UP)
> +		divider_ux1 += rate - 1;
> +
> +	do_div(divider_ux1, rate);
> +
> +	if (flags & TEGRA_DIVIDER_INT)
> +		divider_ux1 *= mul;
> +
> +	divider_ux1 -= mul;
> +
> +	if (divider_ux1 > div_mask(width))
> +		return div_mask(width);
> +
> +	return divider_ux1;
> +}
> 
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kernel test robot July 3, 2018, 3:30 p.m. UTC | #2 
Hi Peter,

I love your patch! Perhaps something to improve:

[auto build test WARNING on tegra/for-next]
[also build test WARNING on v4.18-rc3 next-20180703]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Aapo-Vienamo/clk-tegra-refactor-7-1-div-calculation/20180703-205606
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

   In file included from arch/arm/include/asm/div64.h:127:0,
                    from include/linux/kernel.h:174,
                    from drivers/clk/tegra/div71.c:17:
   drivers/clk/tegra/div71.c: In function 'div71_get':
   include/asm-generic/div64.h:222:28: warning: comparison of distinct pointer types lacks a cast
     (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
                               ^
>> drivers/clk/tegra/div71.c:40:2: note: in expansion of macro 'do_div'
     do_div(divider_ux1, rate);
     ^~~~~~

vim +/do_div +40 drivers/clk/tegra/div71.c

  > 17	#include <linux/kernel.h>
    18	
    19	#include "clk.h"
    20	
    21	#define div_mask(w) ((1 << (w)) - 1)
    22	
    23	int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
    24		      u8 frac_width, u8 flags)
    25	{
    26		s64 divider_ux1 = parent_rate;
    27		int mul;
    28	
    29		if (!rate)
    30			return 0;
    31	
    32		mul = 1 << frac_width;
    33	
    34		if (!(flags & TEGRA_DIVIDER_INT))
    35			divider_ux1 *= mul;
    36	
    37		if (flags & TEGRA_DIVIDER_ROUND_UP)
    38			divider_ux1 += rate - 1;
    39	
  > 40		do_div(divider_ux1, rate);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Aapo Vienamo July 4, 2018, 7:51 a.m. UTC | #3 
On Tue, 3 Jul 2018 11:10:21 -0400
Peter Geis <pgwipeout@gmail.com> wrote:

> Good Morning,
> 
> Just a heads up.
> During compilation with your patches, I get the following warning:
> 
> In file included from ./arch/arm/include/asm/div64.h:127:0,
>                   from ./include/linux/kernel.h:174,
>                   from drivers/clk/tegra/div71.c:17:
> drivers/clk/tegra/div71.c: In function ‘div71_get’:
> ./include/asm-generic/div64.h:222:28: warning: comparison of distinct 
> pointer types lacks a cast
>    (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
>                              ^
> drivers/clk/tegra/div71.c:40:2: note: in expansion of macro ‘do_div’
>    do_div(divider_ux1, rate);
>    ^~~~~~
> 
> Very Respectfully,
> Peter Geis
> 
 
That's indeed true. Looks like this warning is produced only on 32-bit
arm as it uses a different variant of the do_div macro than arm64.

Thanks,
 -Aapo
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Stephen Boyd July 6, 2018, 5:10 p.m. UTC | #4 
Quoting Aapo Vienamo (2018-07-04 00:51:48)
> On Tue, 3 Jul 2018 11:10:21 -0400
> Peter Geis <pgwipeout@gmail.com> wrote:
> 
> > Good Morning,
> > 
> > Just a heads up.
> > During compilation with your patches, I get the following warning:
> > 
> > In file included from ./arch/arm/include/asm/div64.h:127:0,
> >                   from ./include/linux/kernel.h:174,
> >                   from drivers/clk/tegra/div71.c:17:
> > drivers/clk/tegra/div71.c: In function ‘div71_get’:
> > ./include/asm-generic/div64.h:222:28: warning: comparison of distinct 
> > pointer types lacks a cast
> >    (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
> >                              ^
> > drivers/clk/tegra/div71.c:40:2: note: in expansion of macro ‘do_div’
> >    do_div(divider_ux1, rate);
> >    ^~~~~~
> > 
> > Very Respectfully,
> > Peter Geis
> > 
>  
> That's indeed true. Looks like this warning is produced only on 32-bit
> arm as it uses a different variant of the do_div macro than arm64.
> 

divider_ux1 is an s64, but the generic do_div() macro is checking to
make sure that's compatible with a u64, and it isn't. Maybe you should
use a function like div64_long()?

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diff mbox

Patch

diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index b716923..6d4f563 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -24,3 +24,4 @@  obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o
 obj-y					+= cvb.o
 obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o
 obj-$(CONFIG_CLK_TEGRA_BPMP)		+= clk-bpmp.o
+obj-y					+= div71.o
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 16e0aee..ad87858 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -32,35 +32,15 @@ 
 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
 		   unsigned long parent_rate)
 {
-	u64 divider_ux1 = parent_rate;
-	u8 flags = divider->flags;
-	int mul;
-
-	if (!rate)
-		return 0;
-
-	mul = get_mul(divider);
-
-	if (!(flags & TEGRA_DIVIDER_INT))
-		divider_ux1 *= mul;
-
-	if (flags & TEGRA_DIVIDER_ROUND_UP)
-		divider_ux1 += rate - 1;
-
-	do_div(divider_ux1, rate);
-
-	if (flags & TEGRA_DIVIDER_INT)
-		divider_ux1 *= mul;
+	int div;
 
-	divider_ux1 -= mul;
+	div = div71_get(rate, parent_rate, divider->width, divider->frac_width,
+			divider->flags);
 
-	if ((s64)divider_ux1 < 0)
+	if (div < 0)
 		return 0;
 
-	if (divider_ux1 > get_max_div(divider))
-		return get_max_div(divider);
-
-	return divider_ux1;
+	return div;
 }
 
 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e1f8846..f14e136 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -811,6 +811,9 @@  extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
+int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
+	      u8 frac_width, u8 flags);
+
 
 /* Combined read fence with delay */
 #define fence_udelay(delay, reg)	\
diff --git a/drivers/clk/tegra/div71.c b/drivers/clk/tegra/div71.c
new file mode 100644
index 0000000..27b3846
--- /dev/null
+++ b/drivers/clk/tegra/div71.c
@@ -0,0 +1,51 @@ 
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+
+#include "clk.h"
+
+#define div_mask(w) ((1 << (w)) - 1)
+
+int div71_get(unsigned long rate, unsigned parent_rate, u8 width,
+	      u8 frac_width, u8 flags)
+{
+	s64 divider_ux1 = parent_rate;
+	int mul;
+
+	if (!rate)
+		return 0;
+
+	mul = 1 << frac_width;
+
+	if (!(flags & TEGRA_DIVIDER_INT))
+		divider_ux1 *= mul;
+
+	if (flags & TEGRA_DIVIDER_ROUND_UP)
+		divider_ux1 += rate - 1;
+
+	do_div(divider_ux1, rate);
+
+	if (flags & TEGRA_DIVIDER_INT)
+		divider_ux1 *= mul;
+
+	divider_ux1 -= mul;
+
+	if (divider_ux1 > div_mask(width))
+		return div_mask(width);
+
+	return divider_ux1;
+}