Message ID | 1530699455-27654-2-git-send-email-avienamo@nvidia.com (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show |
Quoting Aapo Vienamo (2018-07-04 03:17:34) > diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c > new file mode 100644 > index 0000000..8e19cb3 > --- /dev/null > +++ b/drivers/clk/tegra/clk-sdmmc-mux.c > @@ -0,0 +1,254 @@ > +/* > + * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved. > + * > + * based on clk-mux.c > + > + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> > + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> > + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see <http://www.gnu.org/licenses/>. Any chance we can get SPDX tags here instead of all the boiler plate? > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/err.h> > +#include <linux/types.h> > + > +#include "clk.h" > + > +#define DIV_MASK GENMASK(7, 0) > +#define MUX_SHIFT 29 > +#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT) > + > +#define get_max_div(d) DIV_MASK > +#define get_div_field(val) ((val) & DIV_MASK) > +#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) > + > +static const char * const mux_sdmmc_parents[] = { "pll_p", "pll_c4_out2", > + "pll_c4_out0", "pll_c4_out1", > + "clk_m" }; > +static u8 mux_lj_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6 }; > +static u8 mux_non_lj_idx[] = { [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6 }; These can be const? > + > +static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw) > +{ [...] > +static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate, > + unsigned long parent_rate) > +{ > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > + int div; > + unsigned long flags = 0; > + u32 val; > + u8 src; > + > + div = div71_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); > + if (div < 0) > + return div; > + > + if (sdmmc_mux->lock) > + spin_lock_irqsave(sdmmc_mux->lock, flags); > + > + src = clk_sdmmc_mux_get_parent(hw); > + if (div) > + src = mux_non_lj_idx[src]; > + else > + src = mux_lj_idx[src]; > + > + val = src << MUX_SHIFT; > + val |= div; > + writel(val, sdmmc_mux->reg); > + fence_udelay(2, sdmmc_mux->reg); > + > + if (sdmmc_mux->lock) > + spin_unlock_irqrestore(sdmmc_mux->lock, flags); This conditional locking will give sparse a headache. O well. > + > + return 0; > +} > + > +static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw) > +{ > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > + > + __clk_hw_set_clk(gate_hw, hw); > + > + return gate_ops->is_enabled(gate_hw); > +} > + > +static int clk_sdmmc_mux_enable(struct clk_hw *hw) > +{ > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > + > + __clk_hw_set_clk(gate_hw, hw); > + > + return gate_ops->enable(gate_hw); > +} > + > +static void clk_sdmmc_mux_disable(struct clk_hw *hw) > +{ > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > + > + gate_ops->disable(gate_hw); > +} > + > +const struct clk_ops tegra_clk_sdmmc_mux_ops = { static? > + .get_parent = clk_sdmmc_mux_get_parent, > + .set_parent = clk_sdmmc_mux_set_parent, > + .determine_rate = clk_sdmmc_mux_determine_rate, > + .recalc_rate = clk_sdmmc_mux_recalc_rate, > + .set_rate = clk_sdmmc_mux_set_rate, > + .is_enabled = clk_sdmmc_mux_is_enabled, > + .enable = clk_sdmmc_mux_enable, > + .disable = clk_sdmmc_mux_disable, > +}; > + > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > index f14e136..4c3d0f5 100644 > --- a/drivers/clk/tegra/clk.h > +++ b/drivers/clk/tegra/clk.h > @@ -19,6 +19,7 @@ > > #include <linux/clk-provider.h> > #include <linux/clkdev.h> > +#include <linux/delay.h> Why? Include this in the C file that cares please. > > /** > * struct tegra_clk_sync_source - external clock source from codec -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jul 06, 2018 at 11:18:30AM -0700, Stephen Boyd wrote: > Quoting Aapo Vienamo (2018-07-04 03:17:34) > > diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c > > new file mode 100644 > > index 0000000..8e19cb3 > > --- /dev/null > > +++ b/drivers/clk/tegra/clk-sdmmc-mux.c > > @@ -0,0 +1,254 @@ > > +/* > > + * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved. > > + * > > + * based on clk-mux.c > > + > > + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> > > + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> > > + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > > Any chance we can get SPDX tags here instead of all the boiler plate? > > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/err.h> > > +#include <linux/types.h> > > + > > +#include "clk.h" > > + > > +#define DIV_MASK GENMASK(7, 0) > > +#define MUX_SHIFT 29 > > +#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT) > > + > > +#define get_max_div(d) DIV_MASK > > +#define get_div_field(val) ((val) & DIV_MASK) > > +#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) > > + > > +static const char * const mux_sdmmc_parents[] = { "pll_p", "pll_c4_out2", > > + "pll_c4_out0", "pll_c4_out1", > > + "clk_m" }; > > +static u8 mux_lj_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6 }; > > +static u8 mux_non_lj_idx[] = { [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6 }; > > These can be const? > > > + > > +static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw) > > +{ > [...] > > +static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long parent_rate) > > +{ > > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > > + int div; > > + unsigned long flags = 0; > > + u32 val; > > + u8 src; > > + > > + div = div71_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); > > + if (div < 0) > > + return div; > > + > > + if (sdmmc_mux->lock) > > + spin_lock_irqsave(sdmmc_mux->lock, flags); > > + > > + src = clk_sdmmc_mux_get_parent(hw); > > + if (div) > > + src = mux_non_lj_idx[src]; > > + else > > + src = mux_lj_idx[src]; > > + > > + val = src << MUX_SHIFT; > > + val |= div; > > + writel(val, sdmmc_mux->reg); > > + fence_udelay(2, sdmmc_mux->reg); > > + > > + if (sdmmc_mux->lock) > > + spin_unlock_irqrestore(sdmmc_mux->lock, flags); > > This conditional locking will give sparse a headache. O well. > > > + > > + return 0; > > +} > > + > > +static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw) > > +{ > > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > > + > > + __clk_hw_set_clk(gate_hw, hw); > > + > > + return gate_ops->is_enabled(gate_hw); > > +} > > + > > +static int clk_sdmmc_mux_enable(struct clk_hw *hw) > > +{ > > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > > + > > + __clk_hw_set_clk(gate_hw, hw); > > + > > + return gate_ops->enable(gate_hw); > > +} > > + > > +static void clk_sdmmc_mux_disable(struct clk_hw *hw) > > +{ > > + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); > > + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; > > + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; > > + > > + gate_ops->disable(gate_hw); > > +} > > + > > +const struct clk_ops tegra_clk_sdmmc_mux_ops = { > > static? > > > + .get_parent = clk_sdmmc_mux_get_parent, > > + .set_parent = clk_sdmmc_mux_set_parent, > > + .determine_rate = clk_sdmmc_mux_determine_rate, > > + .recalc_rate = clk_sdmmc_mux_recalc_rate, > > + .set_rate = clk_sdmmc_mux_set_rate, > > + .is_enabled = clk_sdmmc_mux_is_enabled, > > + .enable = clk_sdmmc_mux_enable, > > + .disable = clk_sdmmc_mux_disable, > > +}; > > + > > diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h > > index f14e136..4c3d0f5 100644 > > --- a/drivers/clk/tegra/clk.h > > +++ b/drivers/clk/tegra/clk.h > > @@ -19,6 +19,7 @@ > > > > #include <linux/clk-provider.h> > > #include <linux/clkdev.h> > > +#include <linux/delay.h> > > Why? Include this in the C file that cares please. > The fence_udelay macro uses udelay and is used in clk-sdmmc-mux.c. However it seems more appropriate to include delay.h here rather than in every single user of the macro. Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 6d4f563..916f65b 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -8,6 +8,7 @@ obj-y += clk-periph-fixed.o obj-y += clk-periph-gate.o obj-y += clk-pll.o obj-y += clk-pll-out.o +obj-y += clk-sdmmc-mux.o obj-y += clk-super.o obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c new file mode 100644 index 0000000..8e19cb3 --- /dev/null +++ b/drivers/clk/tegra/clk-sdmmc-mux.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved. + * + * based on clk-mux.c + + * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> + * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/types.h> + +#include "clk.h" + +#define DIV_MASK GENMASK(7, 0) +#define MUX_SHIFT 29 +#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT) + +#define get_max_div(d) DIV_MASK +#define get_div_field(val) ((val) & DIV_MASK) +#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) + +static const char * const mux_sdmmc_parents[] = { "pll_p", "pll_c4_out2", + "pll_c4_out0", "pll_c4_out1", + "clk_m" }; +static u8 mux_lj_idx[] = { [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6 }; +static u8 mux_non_lj_idx[] = { [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6 }; + +static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int num_parents, i; + u32 src, val; + u8 *mux_idx; + + num_parents = clk_hw_get_num_parents(hw); + + val = readl_relaxed(sdmmc_mux->reg); + src = get_mux_field(val); + if (get_div_field(val)) + mux_idx = mux_non_lj_idx; + else + mux_idx = mux_lj_idx; + + for (i = 0; i < num_parents; i++) { + if (mux_idx[i] == src) + return i; + } + + WARN(1, "Unknown parent selector %d\n", src); + + return 0; +} + +static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + u32 val; + + + val = readl_relaxed(sdmmc_mux->reg); + if (get_div_field(val)) + index = mux_non_lj_idx[index]; + else + index = mux_lj_idx[index]; + + val &= ~MUX_MASK; + val |= index << MUX_SHIFT; + + writel(val, sdmmc_mux->reg); + + return 0; +} + +static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + u32 val; + int div, mul; + u64 rate = parent_rate; + + val = readl_relaxed(sdmmc_mux->reg); + div = get_div_field(val); + + mul = 2; + div += mul; + + rate *= mul; + rate += div - 1; + do_div(rate, div); + + return rate; +} + +static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int div, mul; + unsigned long output_rate = req->best_parent_rate; + + req->rate = max(req->rate, req->min_rate); + req->rate = min(req->rate, req->max_rate); + + if (!req->rate) + return output_rate; + + div = div71_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags); + if (div < 0) + div = 0; + + mul = 2; + if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) + req->rate = DIV_ROUND_UP(output_rate * mul, div + mul); + else + req->rate = output_rate * mul / (div + mul); + + return 0; +} + +static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int div; + unsigned long flags = 0; + u32 val; + u8 src; + + div = div71_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); + if (div < 0) + return div; + + if (sdmmc_mux->lock) + spin_lock_irqsave(sdmmc_mux->lock, flags); + + src = clk_sdmmc_mux_get_parent(hw); + if (div) + src = mux_non_lj_idx[src]; + else + src = mux_lj_idx[src]; + + val = src << MUX_SHIFT; + val |= div; + writel(val, sdmmc_mux->reg); + fence_udelay(2, sdmmc_mux->reg); + + if (sdmmc_mux->lock) + spin_unlock_irqrestore(sdmmc_mux->lock, flags); + + return 0; +} + +static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + __clk_hw_set_clk(gate_hw, hw); + + return gate_ops->is_enabled(gate_hw); +} + +static int clk_sdmmc_mux_enable(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + __clk_hw_set_clk(gate_hw, hw); + + return gate_ops->enable(gate_hw); +} + +static void clk_sdmmc_mux_disable(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + gate_ops->disable(gate_hw); +} + +const struct clk_ops tegra_clk_sdmmc_mux_ops = { + .get_parent = clk_sdmmc_mux_get_parent, + .set_parent = clk_sdmmc_mux_set_parent, + .determine_rate = clk_sdmmc_mux_determine_rate, + .recalc_rate = clk_sdmmc_mux_recalc_rate, + .set_rate = clk_sdmmc_mux_set_rate, + .is_enabled = clk_sdmmc_mux_is_enabled, + .enable = clk_sdmmc_mux_enable, + .disable = clk_sdmmc_mux_disable, +}; + +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, + unsigned long flags, void *lock) +{ + struct clk *clk; + struct clk_init_data init; + const struct tegra_clk_periph_regs *bank; + struct tegra_sdmmc_mux *sdmmc_mux; + + init.ops = &tegra_clk_sdmmc_mux_ops; + init.name = name; + init.flags = flags; + init.parent_names = mux_sdmmc_parents; + init.num_parents = ARRAY_SIZE(mux_sdmmc_parents); + + bank = get_reg_bank(clk_num); + if (!bank) + return ERR_PTR(-EINVAL); + + sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL); + if (!sdmmc_mux) + return ERR_PTR(-ENOMEM); + + /* Data in .init is copied by clk_register(), so stack variable OK */ + sdmmc_mux->hw.init = &init; + sdmmc_mux->reg = clk_base + offset; + sdmmc_mux->lock = lock; + sdmmc_mux->gate.clk_base = clk_base; + sdmmc_mux->gate.regs = bank; + sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt; + sdmmc_mux->gate.clk_num = clk_num; + sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB; + sdmmc_mux->div_flags = div_flags; + sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops; + + clk = clk_register(NULL, &sdmmc_mux->hw); + if (IS_ERR(clk)) + return clk; + + sdmmc_mux->gate.hw.clk = clk; + + return clk; +} + diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index f14e136..4c3d0f5 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -19,6 +19,7 @@ #include <linux/clk-provider.h> #include <linux/clkdev.h> +#include <linux/delay.h> /** * struct tegra_clk_sync_source - external clock source from codec @@ -705,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); + +/** + * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling mux and divider + * @flags: hardware-specific flags + * @lock: optional register lock + * @gate: gate clock + * @gate_ops: gate clock ops + */ +struct tegra_sdmmc_mux { + struct clk_hw hw; + void __iomem *reg; + spinlock_t *lock; + const struct clk_ops *gate_ops; + struct tegra_clk_periph_gate gate; + u8 div_flags; +}; + +#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) + +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, + unsigned long flags, void *lock); + /** * struct clk_init_table - clock initialization table * @clk_id: clock id as mentioned in device tree bindings