| Message ID | 1531116302-29921-2-git-send-email-mars.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 9 Jul 2018 14:05:02 +0800 Mars Cheng <mars.cheng@mediatek.com> wrote: > This adds basic chip support for MT6765 SoC. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> M.
On 09/07/18 08:05, Mars Cheng wrote: > This adds basic chip support for MT6765 SoC. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ > arch/arm64/boot/dts/mediatek/mt6765.dtsi | 156 +++++++++++++++++++++++++++ > 3 files changed, 190 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index ac17f60..7506b0d 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb As you can see, we have a long list of SoCs which are poorly supported. I'm not very keen to just add another SoC which supports booting into a ramdisk using the serial console. Do you have a roadmap adding mainline support for this SoC? Regards, Matthias > diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > new file mode 100644 > index 0000000..36dddff2 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +/dts-v1/; > +#include "mt6765.dtsi" > + > +/ { > + model = "MediaTek MT6765 EVB"; > + compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x1e800000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > new file mode 100644 > index 0000000..cc365b1 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > @@ -0,0 +1,156 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "mediatek,mt6765"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x000>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x001>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x002>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x003>; > + }; > + > + cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x101>; > + }; > + > + cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x102>; > + }; > + > + cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x103>; > + }; > + }; > + > + baud_clk: dummy26m { > + compatible = "fixed-clock"; > + clock-frequency = <26000000>; > + #clock-cells = <0>; > + }; > + > + sys_clk: dummyclk { > + compatible = "fixed-clock"; > + clock-frequency = <26000000>; > + #clock-cells = <0>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x2000>, /* GICH */ > + <0 0x0c420000 0 0x20000>; /* GICV */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + sysirq: interrupt-controller@10200a80 { > + compatible = "mediatek,mt6765-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x10200a80 0 0x50>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&baud_clk>, <&sys_clk>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&baud_clk>, <&sys_clk>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + }; /* end of soc */ > +}; >
On 09/07/18 11:20, Matthias Brugger wrote: > > > On 09/07/18 08:05, Mars Cheng wrote: >> This adds basic chip support for MT6765 SoC. >> >> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >> --- >> arch/arm64/boot/dts/mediatek/Makefile | 1 + >> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ >> arch/arm64/boot/dts/mediatek/mt6765.dtsi | 156 +++++++++++++++++++++++++++ >> 3 files changed, 190 insertions(+) >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi >> >> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile >> index ac17f60..7506b0d 100644 >> --- a/arch/arm64/boot/dts/mediatek/Makefile >> +++ b/arch/arm64/boot/dts/mediatek/Makefile >> @@ -1,6 +1,7 @@ >> # SPDX-License-Identifier: GPL-2.0 >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb >> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > > As you can see, we have a long list of SoCs which are poorly supported. > I'm not very keen to just add another SoC which supports booting into a ramdisk > using the serial console. Do you have a roadmap adding mainline support for this > SoC? Yes, that's a valid concern. mt6755 and mt6795 are in a similar state, the latter after three years. I'm all for supporting new SoCs, but this feels looks a box-ticking exercise ("hey, look, our SoC is supported in mainline") which doesn't help anyone. My Ack still stands, but I'd definitely like to see some more complete support before this patch goes in. Thanks, M.
Hi Matthias/Marc On Mon, 2018-07-09 at 17:43 +0100, Marc Zyngier wrote: > On 09/07/18 11:20, Matthias Brugger wrote: > > > > > > On 09/07/18 08:05, Mars Cheng wrote: > >> This adds basic chip support for MT6765 SoC. > >> > >> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > >> --- > >> arch/arm64/boot/dts/mediatek/Makefile | 1 + > >> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ > >> arch/arm64/boot/dts/mediatek/mt6765.dtsi | 156 +++++++++++++++++++++++++++ > >> 3 files changed, 190 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts > >> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi > >> > >> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > >> index ac17f60..7506b0d 100644 > >> --- a/arch/arm64/boot/dts/mediatek/Makefile > >> +++ b/arch/arm64/boot/dts/mediatek/Makefile > >> @@ -1,6 +1,7 @@ > >> # SPDX-License-Identifier: GPL-2.0 > >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > >> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb > >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > >> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > > > > As you can see, we have a long list of SoCs which are poorly supported. > > I'm not very keen to just add another SoC which supports booting into a ramdisk > > using the serial console. Do you have a roadmap adding mainline support for this > > SoC? > > Yes, that's a valid concern. > > mt6755 and mt6795 are in a similar state, the latter after three years. > I'm all for supporting new SoCs, but this feels looks a box-ticking > exercise ("hey, look, our SoC is supported in mainline") which doesn't > help anyone. > > My Ack still stands, but I'd definitely like to see some more complete > support before this patch goes in. > > Thanks, > > M. Yes, we do arrange more resources to do upstream task for mt6765, clk/pinctrl drivers are almost ready to submit. systimer is under reviewing (v9). http://lists.infradead.org/pipermail/linux-mediatek/2018-July/013989.html other drivers including pmic/pwrap/i2c/rtc/kpd/spi/wdt/cqdma/auxadc/pwm/cmdq/disp. We have dedicated owners to handle them and will cowork tightly with members to make sure things happen in the following weeks. For previous chips, we did have no enough support after shell. It is due to fast pace of smartphone SoC and other resource issues. We also know that is no excuse so that we already confirmed owners and their schedules for mt6765. If there is any suggestion, please let us know. Thanks.
On 10/07/18 01:04, Mars Cheng wrote: > Hi Matthias/Marc > > On Mon, 2018-07-09 at 17:43 +0100, Marc Zyngier wrote: >> On 09/07/18 11:20, Matthias Brugger wrote: >>> >>> >>> On 09/07/18 08:05, Mars Cheng wrote: >>>> This adds basic chip support for MT6765 SoC. >>>> >>>> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >>>> --- >>>> arch/arm64/boot/dts/mediatek/Makefile | 1 + >>>> arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ >>>> arch/arm64/boot/dts/mediatek/mt6765.dtsi | 156 +++++++++++++++++++++++++++ >>>> 3 files changed, 190 insertions(+) >>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts >>>> create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile >>>> index ac17f60..7506b0d 100644 >>>> --- a/arch/arm64/boot/dts/mediatek/Makefile >>>> +++ b/arch/arm64/boot/dts/mediatek/Makefile >>>> @@ -1,6 +1,7 @@ >>>> # SPDX-License-Identifier: GPL-2.0 >>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb >>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb >>>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb >>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb >>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb >>>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb >>> >>> As you can see, we have a long list of SoCs which are poorly supported. >>> I'm not very keen to just add another SoC which supports booting into a ramdisk >>> using the serial console. Do you have a roadmap adding mainline support for this >>> SoC? >> >> Yes, that's a valid concern. >> >> mt6755 and mt6795 are in a similar state, the latter after three years. >> I'm all for supporting new SoCs, but this feels looks a box-ticking >> exercise ("hey, look, our SoC is supported in mainline") which doesn't >> help anyone. >> >> My Ack still stands, but I'd definitely like to see some more complete >> support before this patch goes in. >> >> Thanks, >> >> M. > > Yes, we do arrange more resources to do upstream task for mt6765, > clk/pinctrl drivers are almost ready to submit. systimer is under > reviewing (v9). > http://lists.infradead.org/pipermail/linux-mediatek/2018-July/013989.html > > other drivers including > pmic/pwrap/i2c/rtc/kpd/spi/wdt/cqdma/auxadc/pwm/cmdq/disp. We have > dedicated owners to handle them and will cowork tightly with members to > make sure things happen in the following weeks. > Ok, so let's wait until pinctrl driver is submitted. I'd prefer if you could add the clk driver to this series. This way we can get rid of the dummy clocks in the device tree. > For previous chips, we did have no enough support after shell. It is due > to fast pace of smartphone SoC and other resource issues. We also know > that is no excuse so that we already confirmed owners and their > schedules for mt6765. > > If there is any suggestion, please let us know. > I know that smartphone SoC is a fast paced business. Never the less I'm convinced that the basic building blocks won't change much from one version to another. And that mainline support for the previous version of your SoC will help you to get your new drivers faster upstream. For me the best example is the mt7622 which got to a reasonable upstream support quite fast, thanks to a good foundation of mt7623 in mainline. I'd love to see that happen on the smartphone SoCs as well. Not to mention that upstream support will help you internally when you have to rebase your BSP code-base to a new kernel version. That said I think it is good news that you have already defined owner for the different devices and hope to see submissions for them in the near future :) As a suggestion I would say that upstream submission takes time and effort and it will help your engineers if they can allocate some time to do so. But that's most probably a management decision and all engineers know that management bases it's decision on some hard-to-understandable abbreviations like EBITDA etc. ;) Best regards, Matthias
Hi Matthias On Tue, 2018-07-10 at 12:52 +0200, Matthias Brugger wrote: > > On 10/07/18 01:04, Mars Cheng wrote: [...] > > pmic/pwrap/i2c/rtc/kpd/spi/wdt/cqdma/auxadc/pwm/cmdq/disp. We have > > dedicated owners to handle them and will cowork tightly with members to > > make sure things happen in the following weeks. > > > > Ok, so let's wait until pinctrl driver is submitted. I'd prefer if you could add > the clk driver to this series. This way we can get rid of the dummy clocks in > the device tree. > Got it, I will submit this series with clk support in v5. and pinctrl after that. > > For previous chips, we did have no enough support after shell. It is due > > to fast pace of smartphone SoC and other resource issues. We also know > > that is no excuse so that we already confirmed owners and their > > schedules for mt6765. > > > > If there is any suggestion, please let us know. > > > > I know that smartphone SoC is a fast paced business. Never the less I'm > convinced that the basic building blocks won't change much from one version to > another. And that mainline support for the previous version of your SoC will > help you to get your new drivers faster upstream. > > For me the best example is the mt7622 which got to a reasonable upstream support > quite fast, thanks to a good foundation of mt7623 in mainline. I'd love to see > that happen on the smartphone SoCs as well. > > Not to mention that upstream support will help you internally when you have to > rebase your BSP code-base to a new kernel version. > > That said I think it is good news that you have already defined owner for the > different devices and hope to see submissions for them in the near future :) > As a suggestion I would say that upstream submission takes time and effort and > it will help your engineers if they can allocate some time to do so. But that's > most probably a management decision and all engineers know that management bases > it's decision on some hard-to-understandable abbreviations like EBITDA etc. ;) > > Best regards, > Matthias Thanks for your suggestions. We will try to catch up on this mission :-)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index ac17f60..7506b0d 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts new file mode 100644 index 0000000..36dddff2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Mediatek MT6765 + * + * (C) Copyright 2018. Mediatek, Inc. + * + * Mars Cheng <mars.cheng@mediatek.com> + */ + +/dts-v1/; +#include "mt6765.dtsi" + +/ { + model = "MediaTek MT6765 EVB"; + compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi new file mode 100644 index 0000000..cc365b1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Mediatek MT6765 + * + * (C) Copyright 2018. Mediatek, Inc. + * + * Mars Cheng <mars.cheng@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "mediatek,mt6765"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + }; + }; + + baud_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + sys_clk: dummyclk { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x2000>, /* GICH */ + <0 0x0c420000 0 0x20000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt6765-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x50>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6765-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6765-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&baud_clk>, <&sys_clk>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + }; /* end of soc */ +};
This adds basic chip support for MT6765 SoC. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 ++++++ arch/arm64/boot/dts/mediatek/mt6765.dtsi | 156 +++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi