| Message ID | 20180710080114.31469-21-paul.kocialkowski@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jul 10, 2018 at 10:01:12AM +0200, Paul Kocialkowski wrote: > + vpu: video-codec@1c0e000 { > + compatible = "allwinner,sun7i-a20-video-engine"; > + reg = <0x01c0e000 0x1000>; > + The issue is here with all your patches, but you should drop the node label and the extra new line. Maxime
Hi, On Tue, 2018-07-10 at 11:23 +0200, Maxime Ripard wrote: > On Tue, Jul 10, 2018 at 10:01:12AM +0200, Paul Kocialkowski wrote: > > + vpu: video-codec@1c0e000 { > > + compatible = "allwinner,sun7i-a20-video-engine"; > > + reg = <0x01c0e000 0x1000>; > > + > > The issue is here with all your patches, but you should drop the node > label and the extra new line. Noted, this will be fixed in the next revision. Cheers, Paul
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 38999d791cb5..cb6e10196118 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -161,6 +161,21 @@ reg = <0x40000000 0x80000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + cma_pool: cma@4a000000 { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x4a000000 0x6000000>; + reusable; + linux,cma-default; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -466,6 +481,19 @@ }; }; + vpu: video-codec@1c0e000 { + compatible = "allwinner,sun7i-a20-video-engine"; + reg = <0x01c0e000 0x1000>; + + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + + resets = <&ccu RST_VE>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>;
This adds nodes for the Video Engine and the associated reserved memory for the A20. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)