| Message ID | 20180712023337.30112-2-andrew.smirnov@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Jul 11, 2018 at 07:33:36PM -0700, Andrey Smirnov wrote: > Add DT code to explicitly configure PAD_AUD3_BB_CK and avoid relying > on defaults. > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: cphealy@gmail.com > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: Andrew Lunn <andrew@lunn.ch> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Thanks for adding this. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
Hi Andrey, On Wed, Jul 11, 2018 at 11:33 PM, Andrey Smirnov <andrew.smirnov@gmail.com> wrote: > + pinctrl_switch: switchgrp { > + fsl,pins = < > + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 The i.MX51 Reference Manual states that 0xa5 is the default reset value for the register IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK. By reading your commit log I had the impression you wanted to provide the default value explicitly. Please clarify.
On Thu, Jul 12, 2018 at 6:37 AM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Andrey, > > On Wed, Jul 11, 2018 at 11:33 PM, Andrey Smirnov > <andrew.smirnov@gmail.com> wrote: > > > + pinctrl_switch: switchgrp { > > + fsl,pins = < > > + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 > > The i.MX51 Reference Manual states that 0xa5 is the default reset > value for the register IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK. > > By reading your commit log I had the impression you wanted to provide > the default value explicitly. > > Please clarify. I wanted to avoid relying on defaults be it register reset values or settings that bootloader left us with. Default value of 0xa5 works, but, given how the pin is IRQ_TYPE_LEVEL_HIGH, I though it would be better to configure it to have a pulldown. Do you want me to add that to commit log? Thanks, Andrey Smirnov
On Fri, Jul 13, 2018 at 2:15 AM, Andrey Smirnov <andrew.smirnov@gmail.com> wrote: > I wanted to avoid relying on defaults be it register reset values or > settings that bootloader left us with. Default value of 0xa5 works, > but, given how the pin is IRQ_TYPE_LEVEL_HIGH, I though it would be > better to configure it to have a pulldown. Do you want me to add that > to commit log? Yes, that would be nice. Thanks
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 2941a92d40f1..0bb42c00d72b 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
Add DT code to explicitly configure PAD_AUD3_BB_CK and avoid relying on defaults. Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: cphealy@gmail.com Cc: Shawn Guo <shawnguo@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 ++++++++ 1 file changed, 8 insertions(+)