| Message ID | 20180709143524.17480-1-andrew@aj.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10 July 2018 at 00:35, Andrew Jeffery <andrew@aj.id.au> wrote: > The AST2500 SoC family changes the runtime behaviour of the hardware > strapping register (SCU70) to write-1-set/write-1-clear, with > write-1-clear implemented on the "read-only" SoC revision register > (SCU7C). For the the AST2400, the hardware strapping is > runtime-configured with read-modify-write semantics. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au>
On 9 July 2018 at 15:35, Andrew Jeffery <andrew@aj.id.au> wrote: > The AST2500 SoC family changes the runtime behaviour of the hardware > strapping register (SCU70) to write-1-set/write-1-clear, with > write-1-clear implemented on the "read-only" SoC revision register > (SCU7C). For the the AST2400, the hardware strapping is > runtime-configured with read-modify-write semantics. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- Hi -- is this a bugfix suitable for 3.0, or something you'd like to wait until 3.1 ? The commit message sounds like a bugfix... thanks -- PMM
On Fri, 13 Jul 2018, at 01:28, Peter Maydell wrote: > On 9 July 2018 at 15:35, Andrew Jeffery <andrew@aj.id.au> wrote: > > The AST2500 SoC family changes the runtime behaviour of the hardware > > strapping register (SCU70) to write-1-set/write-1-clear, with > > write-1-clear implemented on the "read-only" SoC revision register > > (SCU7C). For the the AST2400, the hardware strapping is > > runtime-configured with read-modify-write semantics. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > Hi -- is this a bugfix suitable for 3.0, or something you'd > like to wait until 3.1 ? The commit message sounds like a bugfix... If we could get it into 3.0 that would be great. I ran into a case where the distinction was important so it would be good to have it resolved sooner rather than later. Cheers, Andrew
On 12 July 2018 at 17:10, Andrew Jeffery <andrew@aj.id.au> wrote: > On Fri, 13 Jul 2018, at 01:28, Peter Maydell wrote: >> On 9 July 2018 at 15:35, Andrew Jeffery <andrew@aj.id.au> wrote: >> > The AST2500 SoC family changes the runtime behaviour of the hardware >> > strapping register (SCU70) to write-1-set/write-1-clear, with >> > write-1-clear implemented on the "read-only" SoC revision register >> > (SCU7C). For the the AST2400, the hardware strapping is >> > runtime-configured with read-modify-write semantics. >> > >> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> >> > --- >> >> Hi -- is this a bugfix suitable for 3.0, or something you'd >> like to wait until 3.1 ? The commit message sounds like a bugfix... > > If we could get it into 3.0 that would be great. I ran into a case where the distinction was important so it would be good to have it resolved sooner rather than later. No problem -- applied to target-arm.next for 3.0 (should go in before rc1). thanks -- PMM
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 5e6d5744eeca..9051767cbbcd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -202,11 +202,26 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, case PROT_KEY: s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0; return; - + case HW_STRAP1: + if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { + s->regs[HW_STRAP1] |= data; + return; + } + /* Jump to assignment below */ + break; + case SILICON_REV: + if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { + s->regs[HW_STRAP1] &= ~data; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + } + /* Avoid assignment below, we've handled everything */ + return; case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: case RNG_DATA: - case SILICON_REV: case FREE_CNTR4: case FREE_CNTR4_EXT: qemu_log_mask(LOG_GUEST_ERROR, diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index d70cc0aeca61..169611a211bb 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -37,6 +37,8 @@ typedef struct AspeedSCUState { #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U +#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) + extern bool is_supported_silicon_rev(uint32_t silicon_rev); #define ASPEED_SCU_PROT_KEY 0x1688A8A8
The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- hw/misc/aspeed_scu.c | 19 +++++++++++++++++-- include/hw/misc/aspeed_scu.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-)