| Message ID | 20180711144131.73552-3-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com> wrote: > Add R7S9210 (RZ/A2) support > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Chris, On Fri, Jul 13, 2018 at 5:50 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com> wrote: > > Add R7S9210 (RZ/A2) support > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Sorry, I spoke too soon. It seems the bindings were never updated for the use of multiple interrupts on RZ/A1. As RZ/A2 adds one new interrupt, can you please document which interrupts are required? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Tuesday, July 17, 2018, Geert Uytterhoeven wrote: > Sorry, I spoke too soon. > It seems the bindings were never updated for the use of multiple > interrupts > on RZ/A1. As RZ/A2 adds one new interrupt, can you please document which > interrupts are required? > Thanks! OK. I will sent and updated patch in a bit. Chris
Hi Geert, On Tuesday, July 17, 2018, Geert Uytterhoeven wrote: > On Fri, Jul 13, 2018 at 5:50 PM Geert Uytterhoeven <geert@linux-m68k.org> > wrote: > > On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com> > wrote: > > > Add R7S9210 (RZ/A2) support > > > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Sorry, I spoke too soon. > It seems the bindings were never updated for the use of multiple > interrupts > on RZ/A1. As RZ/A2 adds one new interrupt, can you please document which > interrupts are required? > Thanks! The issue that I ran into was the device driver assumed some signals were muxed together (TXI and DRI), and that other signals were individual. The existing driver wanted interrupts to be specified in this order: 1. Error 2. RX 3. TX (assumes DRI) 4. Break However, for the SCIF that is present in the RZ/A2M, Error and Break are muxed together, and then DRI is not muxed with TX. This is different than any other SCIF supported by the driver. My solution was to list the Error/Break twice, and then add a new interrupt for DRI. As reference, here is what the DT node would look like: scif0: serial@e8007000 { compatible = "renesas,scif-r7s9210", "renesas,scif"; reg = <0xe8007000 18>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, /* RXI0 */ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* TXI0 */ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* TEI/DRI0 */ clocks = <&mstp4_clks R7S9210_CLK_SCIF0>; clock-names = "fck"; power-domains = <&cpg_clocks>; status = "disabled"; }; Of course I have no problem documenting all this, but I first I just wanted to make sure I was not going to get push back when I submit a DT later that lists the same interrupt twice. Thanks, Chris
Hi Geert, On Tuesday, July 17, 2018, Geert Uytterhoeven wrote: > On Fri, Jul 13, 2018 at 5:50 PM Geert Uytterhoeven <geert@linux-m68k.org> > wrote: > > On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com> > wrote: > > > Add R7S9210 (RZ/A2) support > > > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Sorry, I spoke too soon. > It seems the bindings were never updated for the use of multiple > interrupts > on RZ/A1. As RZ/A2 adds one new interrupt, can you please document which > interrupts are required? > Thanks! The issue that I ran into was the device driver assumed some signals were muxed together (TXI and DRI), and that other signals were individual. The existing driver wanted interrupts to be specified in this order: 1. Error 2. RX 3. TX (assumes DRI) 4. Break However, for the SCIF that is present in the RZ/A2M, Error and Break are muxed together, and then DRI is not muxed with TX. This is different than any other SCIF supported by the driver. My solution was to list the Error/Break twice, and then add a new interrupt for DRI. As reference, here is what the DT node would look like: scif0: serial@e8007000 { compatible = "renesas,scif-r7s9210", "renesas,scif"; reg = <0xe8007000 18>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, /* RXI0 */ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* TXI0 */ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* TEI/DRI0 */ clocks = <&mstp4_clks R7S9210_CLK_SCIF0>; clock-names = "fck"; power-domains = <&cpg_clocks>; status = "disabled"; }; Of course I have no problem documenting all this, but I first I just wanted to make sure I was not going to get push back when I submit a DT later that lists the same interrupt twice. Thanks, Chris
Hi Chris, On Thu, Jul 19, 2018 at 12:19 AM Chris Brandt <Chris.Brandt@renesas.com> wrote: > On Tuesday, July 17, 2018, Geert Uytterhoeven wrote: > > On Fri, Jul 13, 2018 at 5:50 PM Geert Uytterhoeven <geert@linux-m68k.org> > > wrote: > > > On Wed, Jul 11, 2018 at 4:42 PM Chris Brandt <chris.brandt@renesas.com> > > wrote: > > > > Add R7S9210 (RZ/A2) support > > > > > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > Sorry, I spoke too soon. > > It seems the bindings were never updated for the use of multiple > > interrupts > > on RZ/A1. As RZ/A2 adds one new interrupt, can you please document which > > interrupts are required? > > Thanks! > > The issue that I ran into was the device driver assumed some signals > were muxed together (TXI and DRI), and that other signals were individual. > > The existing driver wanted interrupts to be specified in this order: > 1. Error > 2. RX > 3. TX (assumes DRI) > 4. Break Yes, that matches the RZ/A1 SCIFA and interrupt controller docs. > However, for the SCIF that is present in the RZ/A2M, Error and Break are > muxed together, and then DRI is not muxed with TX. This is different > than any other SCIF supported by the driver. Right, the RZ/A2 SCIFA variant is documented to provide 6 interrupt sources: 1. TEI, 2. TXI, 3. RXI, 4. DRI, 5. ERI, 6. BRI. > My solution was to list the Error/Break twice, and then add a new > interrupt for DRI. > > As reference, here is what the DT node would look like: > > scif0: serial@e8007000 { > compatible = "renesas,scif-r7s9210", "renesas,scif"; > reg = <0xe8007000 18>; > interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ > <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, /* RXI0 */ > <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* TXI0 */ > <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI0/BRI0 */ > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* TEI/DRI0 */ > clocks = <&mstp4_clks R7S9210_CLK_SCIF0>; > clock-names = "fck"; > power-domains = <&cpg_clocks>; > status = "disabled"; > }; > > Of course I have no problem documenting all this, but I first I just > wanted to make sure I was not going to get push back when I submit a DT > later that lists the same interrupt twice. Listing them twice does make sense to me, as the interrupt controller source list in the RZ/A2 docs has only four, and explicitly lists how they are multiplexed: base + 0 = ERI/BRI, base + 1 = RXI, base + 2 = TXI, base + 3 = TEI/DRI. But future SoCS with the same SCIFA variant may wire them differently? For DT backwards compatibility, we have to keep support for the following 2 schemes: 1. Single "interrupts" value, no "interrupt-names", for fully multiplexed interrupts (SH/R-Mobile, R-Car). 2. Four "interrupts" values, no "interrupt-names", for ERI/RXI/TXI/TEI (RZ/A1, H8/300). For RZ/A2, I suggest extending the bindings with interrupt-names, documenting all 6 interrupt sources, and let the driver handle that. That means there should be 6, not 5, "interrupts" values. Whether the driver implements all possible combinations, or only what you need for RZ/A2, is up to you. I agree the interrupt handling in the driver is already sufficiently complex. Ideally, you would document support for RZ/A1 with interrupt-names too, and handle that as well. Does this make sense? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, On Thursday, July 19, 2018, Geert Uytterhoeven wrote: > > The issue that I ran into was the device driver assumed some signals > > were muxed together (TXI and DRI), and that other signals were > individual. > > > > The existing driver wanted interrupts to be specified in this order: > > 1. Error > > 2. RX > > 3. TX (assumes DRI) > > 4. Break First, sorry for my mis-type. DRI mean 'Data Ready Interrupt' and for SCIF it is normally muxed with RX (not TX). > > Of course I have no problem documenting all this, but I first I just > > wanted to make sure I was not going to get push back when I submit a DT > > later that lists the same interrupt twice. > > Listing them twice does make sense to me, as the interrupt controller > source list in the RZ/A2 docs has only four, and explicitly lists how they > are > multiplexed: > base + 0 = ERI/BRI, > base + 1 = RXI, > base + 2 = TXI, > base + 3 = TEI/DRI. > But future SoCS with the same SCIFA variant may wire them differently? This SCIF seems to be related to ones used in H8S devices. It's also been used in RX and RZ/T devices. So I think the order seems to be stable. > For DT backwards compatibility, we have to keep support for the following > 2 schemes: > 1. Single "interrupts" value, no "interrupt-names", for fully > multiplexed > interrupts (SH/R-Mobile, R-Car). > 2. Four "interrupts" values, no "interrupt-names", for ERI/RXI/TXI/TEI > (RZ/A1, H8/300). > > For RZ/A2, I suggest extending the bindings with interrupt-names, > documenting all 6 interrupt sources, and let the driver handle that. > That means there should be 6, not 5, "interrupts" values. > Whether the driver implements all possible combinations, or only what you > need for RZ/A2, is up to you. I agree the interrupt handling in the driver > is already sufficiently complex. > Ideally, you would document support for RZ/A1 with interrupt-names too, > and handle that as well. > > Does this make sense? What about this idea: Since we can't break any old DTs, what if we just say that you simply list all the interrupts in DT, and the driver just registers all those vectors with the same ISR function (sci_mpxed_interrupt) and process everything the same way R-Car devices do with their single interrupt. For this class of device, having separate interrupt vectors probably doesn't buy you that much extra performance. The driver could also check to see if "interrupt-names" was specified, and if it was, the driver could simply use those names when registering the interrupts so everything shows up nicely in /proc/interrupts. What's your thoughts on that idea? Chris
Hi Chris, On Thu, Jul 19, 2018 at 2:59 PM Chris Brandt <Chris.Brandt@renesas.com> wrote: > On Thursday, July 19, 2018, Geert Uytterhoeven wrote: > > > The issue that I ran into was the device driver assumed some signals > > > were muxed together (TXI and DRI), and that other signals were > > individual. > > > > > > The existing driver wanted interrupts to be specified in this order: > > > 1. Error > > > 2. RX > > > 3. TX (assumes DRI) > > > 4. Break > > First, sorry for my mis-type. > DRI mean 'Data Ready Interrupt' and for SCIF it is normally muxed with RX (not TX). OK. > > > Of course I have no problem documenting all this, but I first I just > > > wanted to make sure I was not going to get push back when I submit a DT > > > later that lists the same interrupt twice. > > > > Listing them twice does make sense to me, as the interrupt controller > > source list in the RZ/A2 docs has only four, and explicitly lists how they > > are > > multiplexed: > > base + 0 = ERI/BRI, > > base + 1 = RXI, > > base + 2 = TXI, > > base + 3 = TEI/DRI. > > But future SoCS with the same SCIFA variant may wire them differently? > > This SCIF seems to be related to ones used in H8S devices. It's also been > used in RX and RZ/T devices. So I think the order seems to be stable. > > > > For DT backwards compatibility, we have to keep support for the following > > 2 schemes: > > 1. Single "interrupts" value, no "interrupt-names", for fully > > multiplexed > > interrupts (SH/R-Mobile, R-Car). > > 2. Four "interrupts" values, no "interrupt-names", for ERI/RXI/TXI/TEI > > (RZ/A1, H8/300). > > > > For RZ/A2, I suggest extending the bindings with interrupt-names, > > documenting all 6 interrupt sources, and let the driver handle that. > > That means there should be 6, not 5, "interrupts" values. > > Whether the driver implements all possible combinations, or only what you > > need for RZ/A2, is up to you. I agree the interrupt handling in the driver > > is already sufficiently complex. > > Ideally, you would document support for RZ/A1 with interrupt-names too, > > and handle that as well. > > > > Does this make sense? > > What about this idea: > Since we can't break any old DTs, what if we just say that you simply > list all the interrupts in DT, and the driver just registers all those > vectors with the same ISR function (sci_mpxed_interrupt) and process > everything the same way R-Car devices do with their single interrupt. > > For this class of device, having separate interrupt vectors probably > doesn't buy you that much extra performance. > > The driver could also check to see if "interrupt-names" was specified, > and if it was, the driver could simply use those names when registering > the interrupts so everything shows up nicely in /proc/interrupts. > > What's your thoughts on that idea? I don't know if using the same handler for all separate interrupts won't cause problems. What if two interrupts fire, the first one calls the common handler, handles both, and the second one returns IRQ_NONE? Spurious interrupts detected by the core interrupt, leading to "Disabling IRQ #n" once it has seen too many of them? Gr{oetje,eeting}s, Geert
Hi Geert, I have one last clarification about your idea regarding documenting the interrupts separately for RZ/A2. On Thursday, July 19, 2018, Geert Uytterhoeven wrote: > For DT backwards compatibility, we have to keep support for the following > 2 schemes: > 1. Single "interrupts" value, no "interrupt-names", for fully > multiplexed > interrupts (SH/R-Mobile, R-Car). > 2. Four "interrupts" values, no "interrupt-names", for ERI/RXI/TXI/TEI > (RZ/A1, H8/300). > > For RZ/A2, I suggest extending the bindings with interrupt-names, > documenting all 6 interrupt sources, and let the driver handle that. > That means there should be 6, not 5, "interrupts" values. > Whether the driver implements all possible combinations, or only what you > need for RZ/A2, is up to you. I agree the interrupt handling in the driver > is already sufficiently complex. > Ideally, you would document support for RZ/A1 with interrupt-names too, > and handle that as well. So for backward compatibility, no existing DT or setup-xxx.c (SH) file should change and the driver needs to assume the order of interrupts. However, if "interrupt-names" is specified in DT, then the driver determines what the interrupt are based on their names, not the order in which they are listed. Correct? So for example, RZ/A1 DT will stay the same and since "interrupt-names" was never used and the interrupt order will be assumed as ERI/RXI/TXI/BRI. RZ/A1 [ r7s72100.dtsi ] scif0: serial@e8007000 { compatible = "renesas,scif-r7s72100", "renesas,scif"; reg = <0xe8007000 64>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; clock-names = "fck"; power-domains = <&cpg_clocks>; status = "disabled"; }; However, for RZ/A2, "interrupt-names" will be used and then the driver will sort things out however it needs to (figuring out what signals are muxed together an such). RZ/A2 [ r7s9210.dtsi ] scif0: serial@e8007000 { compatible = "renesas,scif-r7s9210", "renesas,scif"; reg = <0xe8007000 18>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI/BRI */ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, /* RXI */ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* TXI */ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI/BRI */ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* TEI/DRI */ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* TEI/DRI */ interrupt-names = "eri", "rxi", "txi", "bri", "tei", "dri"; clocks = <&mstp4_clks R7S9210_CLK_SCIF0>; clock-names = "fck"; power-domains = <&cpg_clocks>; status = "disabled"; }; Are we on the same page? Thanks! Chris
Hi Chris, On Wed, Jul 25, 2018 at 3:38 AM Chris Brandt <Chris.Brandt@renesas.com> wrote: > I have one last clarification about your idea regarding documenting the > interrupts separately for RZ/A2. > > On Thursday, July 19, 2018, Geert Uytterhoeven wrote: > > For DT backwards compatibility, we have to keep support for the following > > 2 schemes: > > 1. Single "interrupts" value, no "interrupt-names", for fully > > multiplexed > > interrupts (SH/R-Mobile, R-Car). > > 2. Four "interrupts" values, no "interrupt-names", for ERI/RXI/TXI/TEI > > (RZ/A1, H8/300). > > > > For RZ/A2, I suggest extending the bindings with interrupt-names, > > documenting all 6 interrupt sources, and let the driver handle that. > > That means there should be 6, not 5, "interrupts" values. > > Whether the driver implements all possible combinations, or only what you > > need for RZ/A2, is up to you. I agree the interrupt handling in the driver > > is already sufficiently complex. > > Ideally, you would document support for RZ/A1 with interrupt-names too, > > and handle that as well. > > So for backward compatibility, no existing DT or setup-xxx.c (SH) file > should change and the driver needs to assume the order of interrupts. You can change the setup-xxx.c (SH) files, if needed. There's no in-kernel stable ABI. > However, if "interrupt-names" is specified in DT, then the driver > determines what the interrupt are based on their names, not the order in which > they are listed. > > Correct? Correct. > So for example, RZ/A1 DT will stay the same and since "interrupt-names" > was never used and the interrupt order will be assumed as > ERI/RXI/TXI/BRI. > > RZ/A1 [ r7s72100.dtsi ] > scif0: serial@e8007000 { > compatible = "renesas,scif-r7s72100", "renesas,scif"; > reg = <0xe8007000 64>; > interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; > clock-names = "fck"; > power-domains = <&cpg_clocks>; > status = "disabled"; > }; Correct. > However, for RZ/A2, "interrupt-names" will be used and then the driver > will sort things out however it needs to (figuring out what signals > are muxed together an such). > > RZ/A2 [ r7s9210.dtsi ] > scif0: serial@e8007000 { > compatible = "renesas,scif-r7s9210", "renesas,scif"; > reg = <0xe8007000 18>; > interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI/BRI */ > <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, /* RXI */ > <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* TXI */ > <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, /* ERI/BRI */ > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* TEI/DRI */ > <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* TEI/DRI */ > interrupt-names = "eri", "rxi", "txi", "bri", "tei", "dri"; > > clocks = <&mstp4_clks R7S9210_CLK_SCIF0>; > clock-names = "fck"; > power-domains = <&cpg_clocks>; > status = "disabled"; > }; Correct. > Are we on the same page? I think so. Thanks! Gr{oetje,eeting}s, Geert
Hi Geert, On Wednesday, July 25, 2018, Geert Uytterhoeven wrote: > > However, if "interrupt-names" is specified in DT, then the driver > > determines what the interrupt are based on their names, not the order in > which > > they are listed. > > > > Correct? > > Correct. One final note on this before I submit v2 of the patch. I just coded up something that works and is more simple and I don't even need "interrupt-names". Basically by using your suggestion from the code review made everything work. On Friday, July 20, 2018, Geert Uytterhoeven wrote: > > --- a/drivers/tty/serial/sh-sci.c > > +++ b/drivers/tty/serial/sh-sci.c > > @@ -65,6 +65,7 @@ enum { > > SCIx_RXI_IRQ, > > SCIx_TXI_IRQ, > > SCIx_BRI_IRQ, > > + SCIx_TEIDRI_IRQ, > > Why not separate enum values for TEI and DRI? According to the RZ/A2 docs, > there are 6 separate interrupts, but they are multiplexed at the interrupt > controller level. enum { SCIx_ERI_IRQ, SCIx_RXI_IRQ, SCIx_TXI_IRQ, SCIx_BRI_IRQ, + SCIx_DRI_IRQ, + SCIx_TEI_IRQ, SCIx_NR_IRQS, SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ }; Listing the same interrupt ID number twice in the DT (because it is muxed) is fine because the driver will check for that. This seems to satisfy all the SCI/SCIF variants in all the SH and ARM SoCs in the kernel today (DT and non-DT). So as long as I describe the interrupt order in the DT Documentation, all seems good. Chris
Hi Chris, On Wed, Jul 25, 2018 at 2:05 PM Chris Brandt <Chris.Brandt@renesas.com> wrote: > On Wednesday, July 25, 2018, Geert Uytterhoeven wrote: > > > However, if "interrupt-names" is specified in DT, then the driver > > > determines what the interrupt are based on their names, not the order in > > which > > > they are listed. > > > > > > Correct? > > > > Correct. > > One final note on this before I submit v2 of the patch. > > I just coded up something that works and is more simple and I don't even > need "interrupt-names". > > Basically by using your suggestion from the code review made everything > work. > > On Friday, July 20, 2018, Geert Uytterhoeven wrote: > > > --- a/drivers/tty/serial/sh-sci.c > > > +++ b/drivers/tty/serial/sh-sci.c > > > @@ -65,6 +65,7 @@ enum { > > > SCIx_RXI_IRQ, > > > SCIx_TXI_IRQ, > > > SCIx_BRI_IRQ, > > > + SCIx_TEIDRI_IRQ, > > > > Why not separate enum values for TEI and DRI? According to the RZ/A2 docs, > > there are 6 separate interrupts, but they are multiplexed at the interrupt > > controller level. > > > enum { > SCIx_ERI_IRQ, > SCIx_RXI_IRQ, > SCIx_TXI_IRQ, > SCIx_BRI_IRQ, > + SCIx_DRI_IRQ, > + SCIx_TEI_IRQ, > SCIx_NR_IRQS, > > SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ > }; > > Listing the same interrupt ID number twice in the DT (because it is > muxed) is fine because the driver will check for that. > > This seems to satisfy all the SCI/SCIF variants in all the SH and ARM > SoCs in the kernel today (DT and non-DT). > > So as long as I describe the interrupt order in the DT Documentation, > all seems good. Yes, that should work too. "interrupt-names" is handy for DTS writers, so they don't have to look up the order in the bindings, and it's less likely they make mistakes in the order of the interrupts. However, as soon as there will be an SoC where you will need a "hole" in the list, you're gonna need interrupt-names anyway. Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 106808b55b6d..5c002bce8f42 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -5,6 +5,7 @@ Required properties: - compatible: Must contain one or more of the following: - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. + - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART. - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
Add R7S9210 (RZ/A2) support Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 1 + 1 file changed, 1 insertion(+)