| Message ID | 20180717095751.1034-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tuesday, July 17, 2018 2:57:50 AM PDT Chris Wilson wrote: > We should we have all the kinks worked out and full-ppgtt now works > reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can > let userspace have full control over their own ppgtt, it makes softpinning > far more effective, in turn making GPU dispatch far more efficient by > virtue of better mm segregation. On the other hand, switching over to a > different GTT for every client does incur noticeable overhead, but only > for very lightweight tasks. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > Cc: Matthew Auld <matthew.william.auld@gmail.com> > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Jason Ekstrand <jason.ekstrand@intel.com> > Cc: Kenneth Graunke <kenneth@whitecape.org> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index f00c7fbef79e..9bad73332ce7 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, > return 0; > } > > - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { > - if (has_full_48bit_ppgtt) > - return 3; > + if (has_full_48bit_ppgtt) > + return 3; > > - if (has_full_ppgtt) > - return 2; > - } > + if (has_full_ppgtt) > + return 2; > > return 1; > } > I'm very glad to see this land, PPGTT is really important for security. It may also enable us to do more interesting things on Gen7.x. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Quoting Kenneth Graunke (2018-07-17 21:02:33) > On Tuesday, July 17, 2018 2:57:50 AM PDT Chris Wilson wrote: > > We should we have all the kinks worked out and full-ppgtt now works > > reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can > > let userspace have full control over their own ppgtt, it makes softpinning > > far more effective, in turn making GPU dispatch far more efficient by > > virtue of better mm segregation. On the other hand, switching over to a > > different GTT for every client does incur noticeable overhead, but only > > for very lightweight tasks. > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Cc: Matthew Auld <matthew.william.auld@gmail.com> > > Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > Cc: Jason Ekstrand <jason.ekstrand@intel.com> > > Cc: Kenneth Graunke <kenneth@whitecape.org> > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++------ > > 1 file changed, 4 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index f00c7fbef79e..9bad73332ce7 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, > > return 0; > > } > > > > - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { > > - if (has_full_48bit_ppgtt) > > - return 3; > > + if (has_full_48bit_ppgtt) > > + return 3; > > > > - if (has_full_ppgtt) > > - return 2; > > - } > > + if (has_full_ppgtt) > > + return 2; > > > > return 1; > > } > > > > I'm very glad to see this land, PPGTT is really important for security. > It may also enable us to do more interesting things on Gen7.x. > > Acked-by: Kenneth Graunke <kenneth@whitecape.org> Plonked in. If I timed it right, it should have just missed the 4.19 cutoff, so we have the best part of 6 months to detect any damage. -Chris
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index f00c7fbef79e..9bad73332ce7 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -179,13 +179,11 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { - if (has_full_48bit_ppgtt) - return 3; + if (has_full_48bit_ppgtt) + return 3; - if (has_full_ppgtt) - return 2; - } + if (has_full_ppgtt) + return 2; return 1; }