| Message ID | 1531746387-7033-11-git-send-email-christoffer.dall@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Christoffer, > -----Original Message----- > From: kvmarm-bounces@lists.cs.columbia.edu [mailto:kvmarm- > bounces@lists.cs.columbia.edu] On Behalf Of Christoffer Dall > Sent: Monday, July 16, 2018 6:36 PM > To: kvmarm@lists.cs.columbia.edu; linux-arm-kernel@lists.infradead.org > Cc: kvm@vger.kernel.org; Marc Zyngier <marc.zyngier@arm.com>; Andre > Przywara <andre.przywara@arm.com> > Subject: [PATCH v4 10/10] KVM: arm/arm64: vgic: Update documentation of > the GIC devices wrt IIDR > > Update the documentation to reflect the ordering requirements of > restoring the GICD_IIDR register before any other registers and the > effects this has on restoring the interrupt groups for an emulated GICv2 > insttance. > > Also remove some outdated limitations in the documentation while we're > at it. > > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > --- > Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ > Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ > 2 files changed, 17 insertions(+), 6 deletions(-) > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > index 2408ab7..eba20ae 100644 > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > @@ -100,6 +100,14 @@ Groups: > Note that distributor fields are not banked, but return the same value > regardless of the mpidr used to access the register. > > + GICD_IIDR.Revision is updated when the KVM implementation is changed > in a > + way directly observable by the guest or userspace. Userspace should > read > + GICD_IIDR from KVM and write back the read value to confirm its > expected > + behavior is aligned with the KVM implementation. Userspace should set > + GICD_IIDR before setting any other registers. to ensure the expected > + behavior. > + > + > The GICD_STATUSR and GICR_STATUSR registers are architecturally > defined such > that a write of a clear bit has no effect, whereas a write with a set bit > clears that value. To allow userspace to freely set the values of these two > diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt > b/Documentation/virtual/kvm/devices/arm-vgic.txt > index b3ce126..4ff7635 100644 > --- a/Documentation/virtual/kvm/devices/arm-vgic.txt > +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt > @@ -49,9 +49,15 @@ Groups: > index is specified with the vcpu_index field. Note that most distributor > fields are not banked, but return the same value regardless of the > vcpu_index used to access the register. > - Limitations: > - - Priorities are not implemented, and registers are RAZ/WI > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > + > + GICD_IIDR.Revision is updated when the KVM implementation of an > emulated > + GICv2 is changed in a way directly observable by the guest or userspace. > + Userspace should read GICD_IIDR from KVM and write back the read > value to > + confirm its expected behavior is aligned with the KVM implementation. > + Userspace should set GICD_IIDR before setting any other registers (both > + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and > KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure > + the expected behavior. Unless GICD_IIDR has been set from userspace, > writes > + to the interrupt group registers (GICD_IGROUPR) are ignored. Newer user-space will write to GICD_IIDR, that mean interrupt-groups are supported otherwise not. And when interrupt-groups are not supported then writes to GICD_IGROUPR are ignored (backward compatibility) Is this understanding correct? Thanks -Bharat > Errors: > -ENXIO: Getting or setting this register is not yet supported > -EBUSY: One or more VCPUs are running > @@ -94,9 +100,6 @@ Groups: > use the lower 5 bits to communicate with the KVM device and must shift > the > value left by 3 places to obtain the actual priority mask level. > > - Limitations: > - - Priorities are not implemented, and registers are RAZ/WI > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > Errors: > -ENXIO: Getting or setting this register is not yet supported > -EBUSY: One or more VCPUs are running > -- > 2.7.4 > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > s.cs.columbia.edu%2Fmailman%2Flistinfo%2Fkvmarm&data=02%7C01% > 7Cbharat.bhushan%40nxp.com%7C55b2ec9f9b7b4d6e530c08d5eb1d0faf%7C > 686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636673432404483929&am > p;sdata=RSQwNKkEYC02igGgPVIQmp40VsC9hU%2FFeiMcQBvYJOA%3D&am > p;reserved=0
On Mon, Jul 16, 2018 at 03:59:42PM +0000, Bharat Bhushan wrote: > Hi Christoffer, > > > -----Original Message----- > > From: kvmarm-bounces@lists.cs.columbia.edu [mailto:kvmarm- > > bounces@lists.cs.columbia.edu] On Behalf Of Christoffer Dall > > Sent: Monday, July 16, 2018 6:36 PM > > To: kvmarm@lists.cs.columbia.edu; linux-arm-kernel@lists.infradead.org > > Cc: kvm@vger.kernel.org; Marc Zyngier <marc.zyngier@arm.com>; Andre > > Przywara <andre.przywara@arm.com> > > Subject: [PATCH v4 10/10] KVM: arm/arm64: vgic: Update documentation of > > the GIC devices wrt IIDR > > > > Update the documentation to reflect the ordering requirements of > > restoring the GICD_IIDR register before any other registers and the > > effects this has on restoring the interrupt groups for an emulated GICv2 > > insttance. > > > > Also remove some outdated limitations in the documentation while we're > > at it. > > > > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > > --- > > Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ > > Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ > > 2 files changed, 17 insertions(+), 6 deletions(-) > > > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > index 2408ab7..eba20ae 100644 > > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > @@ -100,6 +100,14 @@ Groups: > > Note that distributor fields are not banked, but return the same value > > regardless of the mpidr used to access the register. > > > > + GICD_IIDR.Revision is updated when the KVM implementation is changed > > in a > > + way directly observable by the guest or userspace. Userspace should > > read > > + GICD_IIDR from KVM and write back the read value to confirm its > > expected > > + behavior is aligned with the KVM implementation. Userspace should set > > + GICD_IIDR before setting any other registers. to ensure the expected > > + behavior. > > + > > + > > The GICD_STATUSR and GICR_STATUSR registers are architecturally > > defined such > > that a write of a clear bit has no effect, whereas a write with a set bit > > clears that value. To allow userspace to freely set the values of these two > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt > > b/Documentation/virtual/kvm/devices/arm-vgic.txt > > index b3ce126..4ff7635 100644 > > --- a/Documentation/virtual/kvm/devices/arm-vgic.txt > > +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt > > @@ -49,9 +49,15 @@ Groups: > > index is specified with the vcpu_index field. Note that most distributor > > fields are not banked, but return the same value regardless of the > > vcpu_index used to access the register. > > - Limitations: > > - - Priorities are not implemented, and registers are RAZ/WI > > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > > + > > + GICD_IIDR.Revision is updated when the KVM implementation of an > > emulated > > + GICv2 is changed in a way directly observable by the guest or userspace. > > + Userspace should read GICD_IIDR from KVM and write back the read > > value to > > + confirm its expected behavior is aligned with the KVM implementation. > > + Userspace should set GICD_IIDR before setting any other registers (both > > + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and > > KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure > > + the expected behavior. Unless GICD_IIDR has been set from userspace, > > writes > > + to the interrupt group registers (GICD_IGROUPR) are ignored. > > Newer user-space will write to GICD_IIDR, that mean interrupt-groups are supported otherwise not. It only means that userspace can write interrupt groups, interrupt groups will always be supported (and writable) from the guest's point of view with newer kernels. An updated userspace (which writes IIDR) must know to either raise an error if it sees a migration stream from an older QEMU or translate the interrupt groups from 1 to 0 before writing them. > And when interrupt-groups are not supported then writes to GICD_IGROUPR are ignored (backward compatibility) Legacy userspace which doesn't write IIDR will not have the above logic so to preserve migration support between an old kernel and a new kernel, both with legacy userspace, we ignore userspace writes to the IGROUPRs in the KVM interface for userspace which hasn't written IIDR. Hope this helps, -Christoffer
> -----Original Message----- > From: Christoffer Dall [mailto:christoffer.dall@arm.com] > Sent: Tuesday, July 17, 2018 2:44 PM > To: Bharat Bhushan <bharat.bhushan@nxp.com> > Cc: kvmarm@lists.cs.columbia.edu; linux-arm-kernel@lists.infradead.org; > kvm@vger.kernel.org; Marc Zyngier <marc.zyngier@arm.com>; Andre > Przywara <andre.przywara@arm.com> > Subject: Re: [PATCH v4 10/10] KVM: arm/arm64: vgic: Update documentation > of the GIC devices wrt IIDR > > On Mon, Jul 16, 2018 at 03:59:42PM +0000, Bharat Bhushan wrote: > > Hi Christoffer, > > > > > -----Original Message----- > > > From: kvmarm-bounces@lists.cs.columbia.edu [mailto:kvmarm- > > > bounces@lists.cs.columbia.edu] On Behalf Of Christoffer Dall > > > Sent: Monday, July 16, 2018 6:36 PM > > > To: kvmarm@lists.cs.columbia.edu; > > > linux-arm-kernel@lists.infradead.org > > > Cc: kvm@vger.kernel.org; Marc Zyngier <marc.zyngier@arm.com>; > Andre > > > Przywara <andre.przywara@arm.com> > > > Subject: [PATCH v4 10/10] KVM: arm/arm64: vgic: Update documentation > > > of the GIC devices wrt IIDR > > > > > > Update the documentation to reflect the ordering requirements of > > > restoring the GICD_IIDR register before any other registers and the > > > effects this has on restoring the interrupt groups for an emulated > > > GICv2 insttance. > > > > > > Also remove some outdated limitations in the documentation while > > > we're at it. > > > > > > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > > > --- > > > Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ > > > Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ > > > 2 files changed, 17 insertions(+), 6 deletions(-) > > > > > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > > b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > > index 2408ab7..eba20ae 100644 > > > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > > @@ -100,6 +100,14 @@ Groups: > > > Note that distributor fields are not banked, but return the same value > > > regardless of the mpidr used to access the register. > > > > > > + GICD_IIDR.Revision is updated when the KVM implementation is > > > + changed > > > in a > > > + way directly observable by the guest or userspace. Userspace > > > + should > > > read > > > + GICD_IIDR from KVM and write back the read value to confirm its > > > expected > > > + behavior is aligned with the KVM implementation. Userspace should > set > > > + GICD_IIDR before setting any other registers. to ensure the expected > > > + behavior. > > > + > > > + > > > The GICD_STATUSR and GICR_STATUSR registers are architecturally > > > defined such > > > that a write of a clear bit has no effect, whereas a write with a set bit > > > clears that value. To allow userspace to freely set the values > > > of these two diff --git > > > a/Documentation/virtual/kvm/devices/arm-vgic.txt > > > b/Documentation/virtual/kvm/devices/arm-vgic.txt > > > index b3ce126..4ff7635 100644 > > > --- a/Documentation/virtual/kvm/devices/arm-vgic.txt > > > +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt > > > @@ -49,9 +49,15 @@ Groups: > > > index is specified with the vcpu_index field. Note that most distributor > > > fields are not banked, but return the same value regardless of the > > > vcpu_index used to access the register. > > > - Limitations: > > > - - Priorities are not implemented, and registers are RAZ/WI > > > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > > > + > > > + GICD_IIDR.Revision is updated when the KVM implementation of an > > > emulated > > > + GICv2 is changed in a way directly observable by the guest or > userspace. > > > + Userspace should read GICD_IIDR from KVM and write back the > > > + read > > > value to > > > + confirm its expected behavior is aligned with the KVM > implementation. > > > + Userspace should set GICD_IIDR before setting any other registers > (both > > > + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and > > > KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure > > > + the expected behavior. Unless GICD_IIDR has been set from > > > + userspace, > > > writes > > > + to the interrupt group registers (GICD_IGROUPR) are ignored. > > > > Newer user-space will write to GICD_IIDR, that mean interrupt-groups are > supported otherwise not. > > It only means that userspace can write interrupt groups, interrupt groups will > always be supported (and writable) from the guest's point of view with > newer kernels. > > An updated userspace (which writes IIDR) must know to either raise an error > if it sees a migration stream from an older QEMU or translate the interrupt > groups from 1 to 0 before writing them. > > > And when interrupt-groups are not supported then writes to > > GICD_IGROUPR are ignored (backward compatibility) > > Legacy userspace which doesn't write IIDR will not have the above logic so to > preserve migration support between an old kernel and a new kernel, both > with legacy userspace, we ignore userspace writes to the IGROUPRs in the > KVM interface for userspace which hasn't written IIDR. Thanks Christoffer, > > Hope this helps, > -Christoffer
On Mon, Jul 16, 2018 at 03:06:27PM +0200, Christoffer Dall wrote: > Update the documentation to reflect the ordering requirements of > restoring the GICD_IIDR register before any other registers and the > effects this has on restoring the interrupt groups for an emulated GICv2 > insttance. instance > > Also remove some outdated limitations in the documentation while we're > at it. > > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > --- > Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ > Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ > 2 files changed, 17 insertions(+), 6 deletions(-) > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > index 2408ab7..eba20ae 100644 > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > @@ -100,6 +100,14 @@ Groups: > Note that distributor fields are not banked, but return the same value > regardless of the mpidr used to access the register. > > + GICD_IIDR.Revision is updated when the KVM implementation is changed in a > + way directly observable by the guest or userspace. Userspace should read > + GICD_IIDR from KVM and write back the read value to confirm its expected > + behavior is aligned with the KVM implementation. Userspace should set > + GICD_IIDR before setting any other registers. to ensure the expected s/. // > + behavior. > + > + > The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such > that a write of a clear bit has no effect, whereas a write with a set bit > clears that value. To allow userspace to freely set the values of these two > diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt > index b3ce126..4ff7635 100644 > --- a/Documentation/virtual/kvm/devices/arm-vgic.txt > +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt > @@ -49,9 +49,15 @@ Groups: > index is specified with the vcpu_index field. Note that most distributor > fields are not banked, but return the same value regardless of the > vcpu_index used to access the register. > - Limitations: > - - Priorities are not implemented, and registers are RAZ/WI > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > + > + GICD_IIDR.Revision is updated when the KVM implementation of an emulated > + GICv2 is changed in a way directly observable by the guest or userspace. > + Userspace should read GICD_IIDR from KVM and write back the read value to > + confirm its expected behavior is aligned with the KVM implementation. > + Userspace should set GICD_IIDR before setting any other registers (both > + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure > + the expected behavior. Unless GICD_IIDR has been set from userspace, writes > + to the interrupt group registers (GICD_IGROUPR) are ignored. > Errors: > -ENXIO: Getting or setting this register is not yet supported > -EBUSY: One or more VCPUs are running > @@ -94,9 +100,6 @@ Groups: > use the lower 5 bits to communicate with the KVM device and must shift the > value left by 3 places to obtain the actual priority mask level. > > - Limitations: > - - Priorities are not implemented, and registers are RAZ/WI > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > Errors: > -ENXIO: Getting or setting this register is not yet supported > -EBUSY: One or more VCPUs are running > -- > 2.7.4 > Otherwise Reviewed-by: Andrew Jones <drjones@redhat.com>
On Thu, Jul 19, 2018 at 07:08:30PM +0200, Andrew Jones wrote: > On Mon, Jul 16, 2018 at 03:06:27PM +0200, Christoffer Dall wrote: > > Update the documentation to reflect the ordering requirements of > > restoring the GICD_IIDR register before any other registers and the > > effects this has on restoring the interrupt groups for an emulated GICv2 > > insttance. > > instance > > > > > Also remove some outdated limitations in the documentation while we're > > at it. > > > > Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> > > --- > > Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ > > Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ > > 2 files changed, 17 insertions(+), 6 deletions(-) > > > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > index 2408ab7..eba20ae 100644 > > --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt > > @@ -100,6 +100,14 @@ Groups: > > Note that distributor fields are not banked, but return the same value > > regardless of the mpidr used to access the register. > > > > + GICD_IIDR.Revision is updated when the KVM implementation is changed in a > > + way directly observable by the guest or userspace. Userspace should read > > + GICD_IIDR from KVM and write back the read value to confirm its expected > > + behavior is aligned with the KVM implementation. Userspace should set > > + GICD_IIDR before setting any other registers. to ensure the expected > > s/. // > > > + behavior. > > + > > + > > The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such > > that a write of a clear bit has no effect, whereas a write with a set bit > > clears that value. To allow userspace to freely set the values of these two > > diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt > > index b3ce126..4ff7635 100644 > > --- a/Documentation/virtual/kvm/devices/arm-vgic.txt > > +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt > > @@ -49,9 +49,15 @@ Groups: > > index is specified with the vcpu_index field. Note that most distributor > > fields are not banked, but return the same value regardless of the > > vcpu_index used to access the register. > > - Limitations: > > - - Priorities are not implemented, and registers are RAZ/WI > > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > > + > > + GICD_IIDR.Revision is updated when the KVM implementation of an emulated > > + GICv2 is changed in a way directly observable by the guest or userspace. > > + Userspace should read GICD_IIDR from KVM and write back the read value to > > + confirm its expected behavior is aligned with the KVM implementation. > > + Userspace should set GICD_IIDR before setting any other registers (both > > + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure > > + the expected behavior. Unless GICD_IIDR has been set from userspace, writes > > + to the interrupt group registers (GICD_IGROUPR) are ignored. > > Errors: > > -ENXIO: Getting or setting this register is not yet supported > > -EBUSY: One or more VCPUs are running > > @@ -94,9 +100,6 @@ Groups: > > use the lower 5 bits to communicate with the KVM device and must shift the > > value left by 3 places to obtain the actual priority mask level. > > > > - Limitations: > > - - Priorities are not implemented, and registers are RAZ/WI > > - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. > > Errors: > > -ENXIO: Getting or setting this register is not yet supported > > -EBUSY: One or more VCPUs are running > > -- > > 2.7.4 > > > > Otherwise > > Reviewed-by: Andrew Jones <drjones@redhat.com> Thanks. I'm hoping that Marc won't mind fixing this up when applying the patches. -Christoffer
diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt index 2408ab7..eba20ae 100644 --- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt +++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt @@ -100,6 +100,14 @@ Groups: Note that distributor fields are not banked, but return the same value regardless of the mpidr used to access the register. + GICD_IIDR.Revision is updated when the KVM implementation is changed in a + way directly observable by the guest or userspace. Userspace should read + GICD_IIDR from KVM and write back the read value to confirm its expected + behavior is aligned with the KVM implementation. Userspace should set + GICD_IIDR before setting any other registers. to ensure the expected + behavior. + + The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such that a write of a clear bit has no effect, whereas a write with a set bit clears that value. To allow userspace to freely set the values of these two diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt index b3ce126..4ff7635 100644 --- a/Documentation/virtual/kvm/devices/arm-vgic.txt +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt @@ -49,9 +49,15 @@ Groups: index is specified with the vcpu_index field. Note that most distributor fields are not banked, but return the same value regardless of the vcpu_index used to access the register. - Limitations: - - Priorities are not implemented, and registers are RAZ/WI - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. + + GICD_IIDR.Revision is updated when the KVM implementation of an emulated + GICv2 is changed in a way directly observable by the guest or userspace. + Userspace should read GICD_IIDR from KVM and write back the read value to + confirm its expected behavior is aligned with the KVM implementation. + Userspace should set GICD_IIDR before setting any other registers (both + KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS) to ensure + the expected behavior. Unless GICD_IIDR has been set from userspace, writes + to the interrupt group registers (GICD_IGROUPR) are ignored. Errors: -ENXIO: Getting or setting this register is not yet supported -EBUSY: One or more VCPUs are running @@ -94,9 +100,6 @@ Groups: use the lower 5 bits to communicate with the KVM device and must shift the value left by 3 places to obtain the actual priority mask level. - Limitations: - - Priorities are not implemented, and registers are RAZ/WI - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. Errors: -ENXIO: Getting or setting this register is not yet supported -EBUSY: One or more VCPUs are running
Update the documentation to reflect the ordering requirements of restoring the GICD_IIDR register before any other registers and the effects this has on restoring the interrupt groups for an emulated GICv2 insttance. Also remove some outdated limitations in the documentation while we're at it. Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> --- Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 8 ++++++++ Documentation/virtual/kvm/devices/arm-vgic.txt | 15 +++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-)