| Message ID | 20180721090607.7535-1-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Dhinakaran Pandiyan (2018-07-21 10:06:07) > intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers while at > the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am > assuming intel_tile_width_bytes() does the right thing. > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> It's rather that gen2 only has 128B tiling. Note that it only makes any difference for intel_tile_width_bytes().. -Chris
On Sat, 2018-07-21 at 10:11 +0100, Chris Wilson wrote: > Quoting Dhinakaran Pandiyan (2018-07-21 10:06:07) > > > > intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers > > while at > > the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am > > assuming intel_tile_width_bytes() does the right thing. > > > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > It's rather that gen2 only has 128B tiling. Note that it only makes > any > difference for intel_tile_width_bytes().. Okay, the macro is a bit misleading. Do you have any suggestions to clarify it or would you prefer I leave it as it is? > -Chris
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0f49f9988dfa..9b8a4f57a28c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2556,9 +2556,8 @@ intel_info(const struct drm_i915_private *dev_priv) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ - !(IS_I915G(dev_priv) || \ - IS_I915GM(dev_priv))) +#define HAS_128_BYTE_Y_TILING(dev_priv) (!(IS_I915G(dev_priv) || \ + IS_I915GM(dev_priv))) #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers while at the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am assuming intel_tile_width_bytes() does the right thing. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)