diff mbox series

[3/5] drm/i915/icl: Update FIA supported lane count for hpd.

Message ID 20180725002813.6938-4-paulo.r.zanoni@intel.com (mailing list archive)
State New, archived
Headers show
Series Remaining ICL display patches, v2 | expand

Commit Message

Zanoni, Paulo R July 25, 2018, 12:28 a.m. UTC 
From: Animesh Manna <animesh.manna@intel.com>

In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1,
tbt and display controller. In DP alt mode FIA configure the
number of lanes and will be used apart from DPCD read to calculate max
available lanes for DP enablement.

v2 (from Paulo): Simple rebase.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> (v1).
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
[Paulo: significant rewrite of the patch.]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++++++++++++++++++++-
 2 files changed, 35 insertions(+), 1 deletion(-)

Comments

Rodrigo Vivi July 25, 2018, 4:52 p.m. UTC | #1 
On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote:
> From: Animesh Manna <animesh.manna@intel.com>
> 
> In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1,
> tbt and display controller. In DP alt mode FIA configure the
> number of lanes and will be used apart from DPCD read to calculate max
> available lanes for DP enablement.
> 
> v2 (from Paulo): Simple rebase.
> 
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> (v1).
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> [Paulo: significant rewrite of the patch.]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++
>  drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++++++++++++++++++++-
>  2 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 93de6f724e77..72acecaad5c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10705,5 +10705,8 @@ enum skl_power_gate {
>  #define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
>  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
>  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
> +#define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
> +#define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
> +#define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
>  
>  #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 90c5ba6b222b..bb59e71d6f9c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
>  	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
>  }
>  
> +static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> +	u32 lane_info;
> +
> +	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
> +		return 4;
> +
> +	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> +		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> +		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> +
> +	switch (lane_info) {
> +	default:
> +		MISSING_CASE(lane_info);
> +	case 1:
> +	case 2:
> +	case 4:
> +	case 8:
> +		return 1;
> +	case 3:
> +	case 12:
> +		return 2;
> +	case 15:
> +		return 4;

what about replacing this entire switch per a simple

return hweight8(lane_info);

?

> +	}
> +}
> +
>  /* Theoretical max between source and sink */
>  static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	int source_max = intel_dig_port->max_lanes;
>  	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> +	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
>  
> -	return min(source_max, sink_max);
> +	return min3(source_max, sink_max, fia_max);
>  }
>  
>  int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Zanoni, Paulo R July 25, 2018, 5:12 p.m. UTC | #2 
Em Qua, 2018-07-25 às 09:52 -0700, Rodrigo Vivi escreveu:
> On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote:
> > From: Animesh Manna <animesh.manna@intel.com>
> > 
> > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1,
> > tbt and display controller. In DP alt mode FIA configure the
> > number of lanes and will be used apart from DPCD read to calculate
> > max
> > available lanes for DP enablement.
> > 
> > v2 (from Paulo): Simple rebase.
> > 
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> (v1).
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > [Paulo: significant rewrite of the patch.]
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >  drivers/gpu/drm/i915/intel_dp.c | 33
> > ++++++++++++++++++++++++++++++++-
> >  2 files changed, 35 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 93de6f724e77..72acecaad5c1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10705,5 +10705,8 @@ enum skl_power_gate {
> >  #define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
> >  #define   TC_LIVE_STATE_TBT(tc_port)		(1 <<
> > ((tc_port) * 8 + 6))
> >  #define   TC_LIVE_STATE_TC(tc_port)		(1 <<
> > ((tc_port) * 8 + 5))
> > +#define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
> > +#define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf <<
> > ((tc_port) * 8))
> > +#define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port)
> > * 8))
> >  
> >  #endif /* _I915_REG_H_ */
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 90c5ba6b222b..bb59e71d6f9c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct
> > intel_dp *intel_dp)
> >  	return intel_dp->common_rates[intel_dp->num_common_rates -
> > 1];
> >  }
> >  
> > +static int intel_dp_get_fia_supported_lane_count(struct intel_dp
> > *intel_dp)
> > +{
> > +	struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> > +	struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv,
> > dig_port->base.port);
> > +	u32 lane_info;
> > +
> > +	if (tc_port == PORT_TC_NONE || dig_port->tc_type !=
> > TC_PORT_TYPEC)
> > +		return 4;
> > +
> > +	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> > +		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> > +		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> > +
> > +	switch (lane_info) {
> > +	default:
> > +		MISSING_CASE(lane_info);
> > +	case 1:
> > +	case 2:
> > +	case 4:
> > +	case 8:
> > +		return 1;
> > +	case 3:
> > +	case 12:
> > +		return 2;
> > +	case 15:
> > +		return 4;
> 
> what about replacing this entire switch per a simple
> 
> return hweight8(lane_info);
> 
> ?

It kills our ability to hit MISSING_CASE for 5, 6, 7, 9, 10, 11, 13 and
14. I think it's always good to revalidate our hardware/spec
assumptions for the newer platforms (although we don't seem to be
hitting this as far as I have tested).

> 
> > +	}
> > +}
> > +
> >  /* Theoretical max between source and sink */
> >  static int intel_dp_max_common_lane_count(struct intel_dp
> > *intel_dp)
> >  {
> >  	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> >  	int source_max = intel_dig_port->max_lanes;
> >  	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> > +	int fia_max =
> > intel_dp_get_fia_supported_lane_count(intel_dp);
> >  
> > -	return min(source_max, sink_max);
> > +	return min3(source_max, sink_max, fia_max);
> >  }
> >  
> >  int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Rodrigo Vivi July 25, 2018, 5:13 p.m. UTC | #3 
On Wed, Jul 25, 2018 at 09:52:25AM -0700, Rodrigo Vivi wrote:
> On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote:
> > From: Animesh Manna <animesh.manna@intel.com>
> > 
> > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1,
> > tbt and display controller. In DP alt mode FIA configure the
> > number of lanes and will be used apart from DPCD read to calculate max
> > available lanes for DP enablement.
> > 
> > v2 (from Paulo): Simple rebase.
> > 
> > Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> (v1).
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > [Paulo: significant rewrite of the patch.]
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >  drivers/gpu/drm/i915/intel_dp.c | 33 ++++++++++++++++++++++++++++++++-
> >  2 files changed, 35 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 93de6f724e77..72acecaad5c1 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10705,5 +10705,8 @@ enum skl_power_gate {
> >  #define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
> >  #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
> >  #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
> > +#define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
> > +#define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
> > +#define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
> >  
> >  #endif /* _I915_REG_H_ */
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 90c5ba6b222b..bb59e71d6f9c 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -176,14 +176,45 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> >  	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
> >  }
> >  
> > +static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
> > +{
> > +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> > +	u32 lane_info;
> > +
> > +	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
> > +		return 4;
> > +
> > +	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> > +		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> > +		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> > +
> > +	switch (lane_info) {
> > +	default:
> > +		MISSING_CASE(lane_info);
> > +	case 1:
> > +	case 2:
> > +	case 4:
> > +	case 8:
> > +		return 1;
> > +	case 3:
> > +	case 12:
> > +		return 2;
> > +	case 15:
> > +		return 4;
> 
> what about replacing this entire switch per a simple
> 
> return hweight8(lane_info);

ignore this.
specially considering that SOC FW sets these bits, not HW,
I agree that MISSING_CASE is very important.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> ?
> 
> > +	}
> > +}
> > +
> >  /* Theoretical max between source and sink */
> >  static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> >  {
> >  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> >  	int source_max = intel_dig_port->max_lanes;
> >  	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> > +	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
> >  
> > -	return min(source_max, sink_max);
> > +	return min3(source_max, sink_max, fia_max);
> >  }
> >  
> >  int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > -- 
> > 2.17.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 93de6f724e77..72acecaad5c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10705,5 +10705,8 @@  enum skl_power_gate {
 #define PORT_TX_DFLEXDPSP			_MMIO(0x1638A0)
 #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
 #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
+#define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
+#define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
+#define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
 
 #endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 90c5ba6b222b..bb59e71d6f9c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -176,14 +176,45 @@  static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 }
 
+static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
+	u32 lane_info;
+
+	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
+		return 4;
+
+	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
+		     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
+		    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
+
+	switch (lane_info) {
+	default:
+		MISSING_CASE(lane_info);
+	case 1:
+	case 2:
+	case 4:
+	case 8:
+		return 1;
+	case 3:
+	case 12:
+		return 2;
+	case 15:
+		return 4;
+	}
+}
+
 /* Theoretical max between source and sink */
 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	int source_max = intel_dig_port->max_lanes;
 	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
 
-	return min(source_max, sink_max);
+	return min3(source_max, sink_max, fia_max);
 }
 
 int intel_dp_max_lane_count(struct intel_dp *intel_dp)