| Message ID | 20180806144604.8346-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/selftests: Unconditionally do a chipset flush before emit_bb_start | expand |
On 6 August 2018 at 15:46, Chris Wilson <chris@chris-wilson.co.uk> wrote: > Experience teaches us over and over again that coherency on Baytrail > requires the odd heavy hammer, and in particular clflush alone is not > enough to guarrantee that writes from the CPU are picked up by the CS. > Do as we do elsewhere and ensure we have an unconditional > i915_gem_chipset_flush() after writing to memory and submitting a batch > to HW. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107499 > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Quoting Matthew Auld (2018-08-06 19:53:47) > On 6 August 2018 at 15:46, Chris Wilson <chris@chris-wilson.co.uk> wrote: > > Experience teaches us over and over again that coherency on Baytrail > > requires the odd heavy hammer, and in particular clflush alone is not > > enough to guarrantee that writes from the CPU are picked up by the CS. > > Do as we do elsewhere and ensure we have an unconditional > > i915_gem_chipset_flush() after writing to memory and submitting a batch > > to HW. > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107499 > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Reviewed-by: Matthew Auld <matthew.auld@intel.com> Ta. Thanks for checking it over, pushed. -Chris
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 7efb326badcd..e272127783fe 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -906,7 +906,11 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) if (IS_ERR(obj)) return ERR_CAST(obj); - cmd = i915_gem_object_pin_map(obj, I915_MAP_WB); + err = i915_gem_object_set_to_wc_domain(obj, true); + if (err) + goto err; + + cmd = i915_gem_object_pin_map(obj, I915_MAP_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); goto err; @@ -936,13 +940,10 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) } *cmd = MI_BATCH_BUFFER_END; + i915_gem_chipset_flush(i915); i915_gem_object_unpin_map(obj); - err = i915_gem_object_set_to_gtt_domain(obj, false); - if (err) - goto err; - batch = i915_vma_instance(obj, vma->vm, NULL); if (IS_ERR(batch)) { err = PTR_ERR(batch);
Experience teaches us over and over again that coherency on Baytrail requires the odd heavy hammer, and in particular clflush alone is not enough to guarrantee that writes from the CPU are picked up by the CS. Do as we do elsewhere and ensure we have an unconditional i915_gem_chipset_flush() after writing to memory and submitting a batch to HW. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107499 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/selftests/huge_pages.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)