| Message ID | 20180814102740.30222-4-vivek.gautam@codeaurora.org (mailing list archive) |
|---|---|
| State | Deferred, archived |
| Delegated to: | Andy Gross |
| Headers | show |
| Series | Enable smmu support on sdm845 | expand |
Hi Vivek, On 14/08/18 11:27, Vivek Gautam wrote: > Add device node for qcom,smmu-v2 available on sdm845. > This smmu is available only to GPU device. > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 1c2be2082f33..bd1ec5fa5146 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -6,6 +6,7 @@ > */ > > #include <dt-bindings/clock/qcom,gcc-sdm845.h> > +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > @@ -989,6 +990,28 @@ > cell-index = <0>; > }; > > + gpu_smmu: iommu@5040000 { > + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; Which of "sdm845" or "msm8996"[1] is the actual SoC name here? Robin. [1] https://www.mail-archive.com/freedreno@lists.freedesktop.org/msg02659.html > + reg = <0x5040000 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; > + clock-names = "bus", "iface"; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>; > + > + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; > reg = <0x15000000 0x80000>; >
Adding Jordan here. On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: > Hi Vivek, > > On 14/08/18 11:27, Vivek Gautam wrote: >> >> Add device node for qcom,smmu-v2 available on sdm845. >> This smmu is available only to GPU device. >> >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> index 1c2be2082f33..bd1ec5fa5146 100644 >> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> @@ -6,6 +6,7 @@ >> */ >> #include <dt-bindings/clock/qcom,gcc-sdm845.h> >> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >> #include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> @@ -989,6 +990,28 @@ >> cell-index = <0>; >> }; >> + gpu_smmu: iommu@5040000 { >> + compatible = "qcom,sdm845-smmu-v2", >> "qcom,smmu-v2"; > > > Which of "sdm845" or "msm8996"[1] is the actual SoC name here? Well, the bindings use the SoC prefix with smmu-v2, so it should be sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. Using 8996 based string in sdm845 makes things look awful. Thanks Vivek [2] https://patchwork.kernel.org/patch/10534989/ > > Robin. > > [1] > https://www.mail-archive.com/freedreno@lists.freedesktop.org/msg02659.html > >> + reg = <0x5040000 0x10000>; >> + #iommu-cells = <1>; >> + #global-interrupts = <2>; >> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, >> + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; >> + clock-names = "bus", "iface"; >> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gcc GCC_GPU_CFG_AHB_CLK>; >> + >> + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ >> + }; >> + >> apps_smmu: iommu@15000000 { >> compatible = "qcom,sdm845-smmu-500", >> "arm,mmu-500"; >> reg = <0x15000000 0x80000>; >> > _______________________________________________ > iommu mailing list > iommu@lists.linux-foundation.org > https://lists.linuxfoundation.org/mailman/listinfo/iommu
On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: > Adding Jordan here. > > On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: > > Hi Vivek, > > > > On 14/08/18 11:27, Vivek Gautam wrote: > >> > >> Add device node for qcom,smmu-v2 available on sdm845. > >> This smmu is available only to GPU device. > >> > >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > >> --- > >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ > >> 1 file changed, 23 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> b/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> index 1c2be2082f33..bd1ec5fa5146 100644 > >> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > >> @@ -6,6 +6,7 @@ > >> */ > >> #include <dt-bindings/clock/qcom,gcc-sdm845.h> > >> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> > >> #include <dt-bindings/clock/qcom,rpmh.h> > >> #include <dt-bindings/interrupt-controller/arm-gic.h> > >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> > >> @@ -989,6 +990,28 @@ > >> cell-index = <0>; > >> }; > >> + gpu_smmu: iommu@5040000 { > >> + compatible = "qcom,sdm845-smmu-v2", > >> "qcom,smmu-v2"; > > > > > > Which of "sdm845" or "msm8996"[1] is the actual SoC name here? > > Well, the bindings use the SoC prefix with smmu-v2, so it should be > sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. > Using 8996 based string in sdm845 makes things look awful. You need to list valid values of '<soc>' in the binding. Otherwise we get this confusion. Rob
Hi Rob, Robin, On 8/15/2018 4:27 AM, Rob Herring wrote: > On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: >> Adding Jordan here. >> >> On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> wrote: >>> Hi Vivek, >>> >>> On 14/08/18 11:27, Vivek Gautam wrote: >>>> Add device node for qcom,smmu-v2 available on sdm845. >>>> This smmu is available only to GPU device. >>>> >>>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >>>> --- >>>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >>>> 1 file changed, 23 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> index 1c2be2082f33..bd1ec5fa5146 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>> @@ -6,6 +6,7 @@ >>>> */ >>>> #include <dt-bindings/clock/qcom,gcc-sdm845.h> >>>> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >>>> #include <dt-bindings/clock/qcom,rpmh.h> >>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>> @@ -989,6 +990,28 @@ >>>> cell-index = <0>; >>>> }; >>>> + gpu_smmu: iommu@5040000 { >>>> + compatible = "qcom,sdm845-smmu-v2", >>>> "qcom,smmu-v2"; >>> >>> Which of "sdm845" or "msm8996"[1] is the actual SoC name here? >> Well, the bindings use the SoC prefix with smmu-v2, so it should be >> sdm845 for this SoC. This is same as I posted in my v1 of the series [2]. >> Using 8996 based string in sdm845 makes things look awful. > You need to list valid values of '<soc>' in the binding. Otherwise we > get this confusion. Sorry for delayed response, I was away on vacation. I will list down the valid values for '<soc>' as suggested, and respin this series, and smmu bindings patch that comes as part of the runtime pm series [1]. [1] https://lore.kernel.org/patchwork/patch/968017/ Best regards Vivek > > Rob
On 8/27/2018 2:26 PM, Vivek Gautam wrote: > Hi Rob, Robin, > > > On 8/15/2018 4:27 AM, Rob Herring wrote: >> On Wed, Aug 15, 2018 at 01:09:43AM +0530, Vivek Gautam wrote: >>> Adding Jordan here. >>> >>> On Tue, Aug 14, 2018 at 4:19 PM, Robin Murphy <robin.murphy@arm.com> >>> wrote: >>>> Hi Vivek, >>>> >>>> On 14/08/18 11:27, Vivek Gautam wrote: >>>>> Add device node for qcom,smmu-v2 available on sdm845. >>>>> This smmu is available only to GPU device. >>>>> >>>>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ >>>>> 1 file changed, 23 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> index 1c2be2082f33..bd1ec5fa5146 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>> @@ -6,6 +6,7 @@ >>>>> */ >>>>> #include <dt-bindings/clock/qcom,gcc-sdm845.h> >>>>> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> >>>>> #include <dt-bindings/clock/qcom,rpmh.h> >>>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>>> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >>>>> @@ -989,6 +990,28 @@ >>>>> cell-index = <0>; >>>>> }; >>>>> + gpu_smmu: iommu@5040000 { >>>>> + compatible = "qcom,sdm845-smmu-v2", >>>>> "qcom,smmu-v2"; >>>> >>>> Which of "sdm845" or "msm8996"[1] is the actual SoC name here? >>> Well, the bindings use the SoC prefix with smmu-v2, so it should be >>> sdm845 for this SoC. This is same as I posted in my v1 of the series >>> [2]. >>> Using 8996 based string in sdm845 makes things look awful. >> You need to list valid values of '<soc>' in the binding. Otherwise we >> get this confusion. > > Sorry for delayed response, I was away on vacation. > I will list down the valid values for '<soc>' as suggested, and respin > this series, and > smmu bindings patch that comes as part of the runtime pm series [3]. > > [3] https://lore.kernel.org/patchwork/patch/968017/ > I have updated the binding doc with valid values for '<soc>' string [4]. Kindly review this based on [4]. [4] https://lore.kernel.org/patchwork/patch/977888/ Best regards Vivek
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1c2be2082f33..bd1ec5fa5146 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,gpucc-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -989,6 +990,28 @@ cell-index = <0>; }; + gpu_smmu: iommu@5040000 { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clock-names = "bus", "iface"; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + + /*power-domains = <&gpucc GPU_CX_GDSC>;*/ + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; reg = <0x15000000 0x80000>;
Add device node for qcom,smmu-v2 available on sdm845. This smmu is available only to GPU device. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)