diff mbox series

[06/13] coresight: etb10: Handle errors enabling the device

Message ID 1533562915-21558-7-git-send-email-suzuki.poulose@arm.com (mailing list archive)
State New, archived
Headers show
Series coresight: Implement device claim protocol | expand

Commit Message

Suzuki K Poulose Aug. 6, 2018, 1:41 p.m. UTC
Prepare the etb10 driver to return errors in enabling
the device.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-etb10.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

Comments

Mathieu Poirier Aug. 14, 2018, 5:40 p.m. UTC | #1
Hi Suzuki,

On Mon, Aug 06, 2018 at 02:41:48PM +0100, Suzuki K Poulose wrote:
> Prepare the etb10 driver to return errors in enabling
> the device.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etb10.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
> index 9fd77fd..37d2c88 100644
> --- a/drivers/hwtracing/coresight/coresight-etb10.c
> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
> @@ -107,7 +107,7 @@ static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
>  	return depth;
>  }
>  
> -static void etb_enable_hw(struct etb_drvdata *drvdata)
> +static void __etb_enable_hw(struct etb_drvdata *drvdata)
>  {
>  	int i;
>  	u32 depth;
> @@ -135,6 +135,12 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
>  	CS_LOCK(drvdata->base);
>  }
>  
> +static int etb_enable_hw(struct etb_drvdata *drvdata)
> +{
> +	__etb_enable_hw(drvdata);
> +	return 0;
> +}
> +
>  static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  {
>  	int ret = 0;
> @@ -150,7 +156,7 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  	if (mode == CS_MODE_PERF) {
>  		ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
>  		if (ret)
> -			goto out;
> +			return ret;
>  	}
>  
>  	val = local_cmpxchg(&drvdata->mode,
> @@ -172,12 +178,14 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  		goto out;
>  
>  	spin_lock_irqsave(&drvdata->spinlock, flags);
> -	etb_enable_hw(drvdata);
> +	ret = etb_enable_hw(drvdata);
>  	spin_unlock_irqrestore(&drvdata->spinlock, flags);
>  
> -out:
> -	if (!ret)
> +	if (ret)
> +		local_cmpxchg(&drvdata->mode, mode, CS_MODE_DISABLED);
> +	else

I also have to do hackish things with my work on
CPU-wide trace scenarios because drvdata->mode is of type local_t.  Instead of
living with it I'll send out a patch later today that moves it to a u32 like ETF
and ETR.

Please look at it and if you're happy, add it to this patchset and do your 
modifications on top of it.

Thanks,
Mathieu

>  		dev_dbg(drvdata->dev, "ETB enabled\n");
> +
>  	return ret;
>  }
>  
> -- 
> 2.7.4
>
Mathieu Poirier Aug. 15, 2018, 7:38 p.m. UTC | #2
On Mon, Aug 06, 2018 at 02:41:48PM +0100, Suzuki K Poulose wrote:
> Prepare the etb10 driver to return errors in enabling
> the device.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etb10.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
> index 9fd77fd..37d2c88 100644
> --- a/drivers/hwtracing/coresight/coresight-etb10.c
> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
> @@ -107,7 +107,7 @@ static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
>  	return depth;
>  }
>  
> -static void etb_enable_hw(struct etb_drvdata *drvdata)
> +static void __etb_enable_hw(struct etb_drvdata *drvdata)
>  {
>  	int i;
>  	u32 depth;
> @@ -135,6 +135,12 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
>  	CS_LOCK(drvdata->base);
>  }
>  
> +static int etb_enable_hw(struct etb_drvdata *drvdata)
> +{
> +	__etb_enable_hw(drvdata);
> +	return 0;
> +}
> +
>  static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  {
>  	int ret = 0;
> @@ -150,7 +156,7 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  	if (mode == CS_MODE_PERF) {
>  		ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
>  		if (ret)
> -			goto out;
> +			return ret;
>  	}
>  
>  	val = local_cmpxchg(&drvdata->mode,
> @@ -172,12 +178,14 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>  		goto out;

Leaving this here doesn't compile when 'out' is removed below.

>  
>  	spin_lock_irqsave(&drvdata->spinlock, flags);
> -	etb_enable_hw(drvdata);
> +	ret = etb_enable_hw(drvdata);
>  	spin_unlock_irqrestore(&drvdata->spinlock, flags);
>  
> -out:
> -	if (!ret)
> +	if (ret)
> +		local_cmpxchg(&drvdata->mode, mode, CS_MODE_DISABLED);
> +	else
>  		dev_dbg(drvdata->dev, "ETB enabled\n");
> +
>  	return ret;
>  }
>  
> -- 
> 2.7.4
>
Suzuki K Poulose Aug. 16, 2018, 3:46 p.m. UTC | #3
On 15/08/18 20:38, Mathieu Poirier wrote:
> On Mon, Aug 06, 2018 at 02:41:48PM +0100, Suzuki K Poulose wrote:
>> Prepare the etb10 driver to return errors in enabling
>> the device.
>>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-etb10.c | 18 +++++++++++++-----
>>   1 file changed, 13 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
>> index 9fd77fd..37d2c88 100644
>> --- a/drivers/hwtracing/coresight/coresight-etb10.c
>> +++ b/drivers/hwtracing/coresight/coresight-etb10.c
>> @@ -107,7 +107,7 @@ static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
>>   	return depth;
>>   }
>>   
>> -static void etb_enable_hw(struct etb_drvdata *drvdata)
>> +static void __etb_enable_hw(struct etb_drvdata *drvdata)
>>   {
>>   	int i;
>>   	u32 depth;
>> @@ -135,6 +135,12 @@ static void etb_enable_hw(struct etb_drvdata *drvdata)
>>   	CS_LOCK(drvdata->base);
>>   }
>>   
>> +static int etb_enable_hw(struct etb_drvdata *drvdata)
>> +{
>> +	__etb_enable_hw(drvdata);
>> +	return 0;
>> +}
>> +
>>   static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>>   {
>>   	int ret = 0;
>> @@ -150,7 +156,7 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>>   	if (mode == CS_MODE_PERF) {
>>   		ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
>>   		if (ret)
>> -			goto out;
>> +			return ret;
>>   	}
>>   
>>   	val = local_cmpxchg(&drvdata->mode,
>> @@ -172,12 +178,14 @@ static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
>>   		goto out;
> 
> Leaving this here doesn't compile when 'out' is removed below.

I will fix it for arm32. Sorry about that.

Suzuki
diff mbox series

Patch

diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 9fd77fd..37d2c88 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -107,7 +107,7 @@  static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
 	return depth;
 }
 
-static void etb_enable_hw(struct etb_drvdata *drvdata)
+static void __etb_enable_hw(struct etb_drvdata *drvdata)
 {
 	int i;
 	u32 depth;
@@ -135,6 +135,12 @@  static void etb_enable_hw(struct etb_drvdata *drvdata)
 	CS_LOCK(drvdata->base);
 }
 
+static int etb_enable_hw(struct etb_drvdata *drvdata)
+{
+	__etb_enable_hw(drvdata);
+	return 0;
+}
+
 static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
 {
 	int ret = 0;
@@ -150,7 +156,7 @@  static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
 	if (mode == CS_MODE_PERF) {
 		ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
 		if (ret)
-			goto out;
+			return ret;
 	}
 
 	val = local_cmpxchg(&drvdata->mode,
@@ -172,12 +178,14 @@  static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
 		goto out;
 
 	spin_lock_irqsave(&drvdata->spinlock, flags);
-	etb_enable_hw(drvdata);
+	ret = etb_enable_hw(drvdata);
 	spin_unlock_irqrestore(&drvdata->spinlock, flags);
 
-out:
-	if (!ret)
+	if (ret)
+		local_cmpxchg(&drvdata->mode, mode, CS_MODE_DISABLED);
+	else
 		dev_dbg(drvdata->dev, "ETB enabled\n");
+
 	return ret;
 }