| Message ID | 1534515531-20599-8-git-send-email-uma.shankar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Plane Color Properties | expand |
Hi Uma, On Fri, Aug 17, 2018 at 07:48:50PM +0530, Uma Shankar wrote: > Implement Plane Gamma feature for BDW and Gen9 platforms. > > v2: Used newly added drm_color_lut_ext structure for enhanced > precision for Gamma LUT entries. > > v3: Rebase > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 5 +++- > drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++ > drivers/gpu/drm/i915/intel_color.c | 58 ++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_display.c | 4 +++ > drivers/gpu/drm/i915/intel_sprite.c | 4 +++ > 5 files changed, 95 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index e931b48..40de78c 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -54,7 +54,10 @@ > .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } > > #define BDW_COLORS \ > - .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } > + .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \ > + .plane_color = { .plane_degamma_lut_size = 0, \ > + .plane_gamma_lut_size = 16 } > + > #define CHV_COLORS \ > .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } > #define GLK_COLORS \ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0c9f03d..2db6a84 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -172,6 +172,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > +/* Plane Gamma Registers */ > +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) > +#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) > + > #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) > #define _MASKED_FIELD(mask, value) ({ \ > if (__builtin_constant_p(mask)) \ > @@ -9713,6 +9717,27 @@ enum skl_power_gate { > #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) > #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) > > +/* Plane Gamma in Gen9+ */ > +#define _PLANE_GAMC_1_A 0x701d0 > +#define _PLANE_GAMC_1_B 0x711d0 > +#define _PLANE_GAMC_2_A 0x702d0 > +#define _PLANE_GAMC_2_B 0x712d0 > +#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B) > +#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B) > +#define PLANE_GAMC(pipe, plane, i) \ > + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe)) > + > +#define _PLANE_GAMC16_1_A 0x70210 > +#define _PLANE_GAMC16_1_B 0x71210 > +#define _PLANE_GAMC16_2_A 0x70310 > +#define _PLANE_GAMC16_2_B 0x71310 > +#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \ > + _PLANE_GAMC16_1_B) > +#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \ > + _PLANE_GAMC16_2_B) > +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ > + _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) > + > /* pipe CSC & degamma/gamma LUTs on CHV */ > #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) > #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index fb8402f..2b5c0cd 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -492,6 +492,59 @@ static void broadwell_load_luts(struct drm_crtc_state *state) > I915_WRITE(PREC_PAL_INDEX(pipe), 0); > } > > +static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, > + u32 offset) > +{ > + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); > + enum pipe pipe = to_intel_plane(state->plane)->pipe; > + enum plane_id plane = to_intel_plane(state->plane)->id; > + uint32_t i, lut_size = > + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size; > + > + if (state->gamma_lut) { > + struct drm_color_lut_ext *lut = > + (struct drm_color_lut_ext *) state->gamma_lut->data; > + > + for (i = 0; i < lut_size; i++) { > + uint32_t word = > + (drm_color_lut_extract(lut[i].red, 10) << 20) | > + (drm_color_lut_extract(lut[i].green, 10) << 10) | > + drm_color_lut_extract(lut[i].blue, 10); Shouldn't you be using drm_color_lut_extract_ext ? > + > + I915_WRITE(PLANE_GAMC(pipe, plane, i), word); > + } > + > + /* Program the max register to clamp values > 1.0. */ > + i = lut_size - 1; > + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), > + drm_color_lut_extract(lut[i].red, 16)); > + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), > + drm_color_lut_extract(lut[i].green, 16)); > + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), > + drm_color_lut_extract(lut[i].blue, 16)); > + } else { > + for (i = 0; i < lut_size; i++) { > + uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); > + > + I915_WRITE(PLANE_GAMC(pipe, plane, i), > + (v << 20) | (v << 10) | v); > + } > + > + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1); > + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1); > + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1); > + } > +} > + > +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ > +static void broadwell_load_plane_luts(const struct drm_plane_state *state) > +{ > + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); > + > + bdw_load_plane_gamma_lut(state, > + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); > +} > + > static void glk_load_degamma_lut(struct drm_crtc_state *state) > { > struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); > @@ -648,6 +701,11 @@ void intel_plane_color_init(struct drm_plane *plane) > > drm_plane_color_create_prop(plane->dev, plane); > > + if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || > + IS_BROXTON(dev_priv)) { > + dev_priv->display.load_plane_luts = broadwell_load_plane_luts; > + } > + > /* Enable color management support when we have degamma & gamma LUTs. */ > if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 && > INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 690e1e8..2d15ac2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -13803,6 +13803,10 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv, > DRM_COLOR_YCBCR_BT709, > DRM_COLOR_YCBCR_LIMITED_RANGE); > > + /* Add Plane Color properties */ > + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) > + intel_plane_color_init(&primary->base); > + > drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); > > return primary; > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index f7026e8..0eeb1d3 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -1650,6 +1650,10 @@ struct intel_plane * > DRM_COLOR_YCBCR_BT709, > DRM_COLOR_YCBCR_LIMITED_RANGE); > > + /* Add Plane Color properties */ > + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) > + intel_plane_color_init(&intel_plane->base); > + > drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); > > return intel_plane; > -- > 1.9.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>-----Original Message----- >From: Alexandru-Cosmin Gheorghe [mailto:Alexandru- >Cosmin.Gheorghe@arm.com] >Sent: Tuesday, August 21, 2018 3:26 PM >To: Shankar, Uma <uma.shankar@intel.com> >Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; >dcastagna@chromium.org; emil.l.velikov@gmail.com; seanpaul@chromium.org; >Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten ><maarten.lankhorst@intel.com>; nd@arm.com >Subject: Re: [RFC v4 7/8] drm/i915: Implement Plane Gamma for Bdw and Gen9 >platforms > >Hi Uma, > >On Fri, Aug 17, 2018 at 07:48:50PM +0530, Uma Shankar wrote: >> Implement Plane Gamma feature for BDW and Gen9 platforms. >> >> v2: Used newly added drm_color_lut_ext structure for enhanced >> precision for Gamma LUT entries. >> >> v3: Rebase >> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com> >> --- >> drivers/gpu/drm/i915/i915_pci.c | 5 +++- >> drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++ >> drivers/gpu/drm/i915/intel_color.c | 58 >++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_display.c | 4 +++ >> drivers/gpu/drm/i915/intel_sprite.c | 4 +++ >> 5 files changed, 95 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c >> b/drivers/gpu/drm/i915/i915_pci.c index e931b48..40de78c 100644 >> --- a/drivers/gpu/drm/i915/i915_pci.c >> +++ b/drivers/gpu/drm/i915/i915_pci.c >> @@ -54,7 +54,10 @@ >> .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, >> IVB_CURSOR_C_OFFSET } >> >> #define BDW_COLORS \ >> - .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } >> + .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \ >> + .plane_color = { .plane_degamma_lut_size = 0, \ >> + .plane_gamma_lut_size = 16 } >> + >> #define CHV_COLORS \ >> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } #define >> GLK_COLORS \ diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h index 0c9f03d..2db6a84 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -172,6 +172,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t >> reg) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define >> _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) >> >> +/* Plane Gamma Registers */ >> +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + >> +(i) * 4) #define _MMIO_PLANE_GAMC16(plane, i, a, b) >> +_MMIO(_PIPE(plane, a, b) + (i) * 4) >> + >> #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) >> #define _MASKED_FIELD(mask, value) ({ > \ >> if (__builtin_constant_p(mask)) \ >> @@ -9713,6 +9717,27 @@ enum skl_power_gate { >> #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, >_PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) >> #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, >_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) >> >> +/* Plane Gamma in Gen9+ */ >> +#define _PLANE_GAMC_1_A 0x701d0 >> +#define _PLANE_GAMC_1_B 0x711d0 >> +#define _PLANE_GAMC_2_A 0x702d0 >> +#define _PLANE_GAMC_2_B 0x712d0 >> +#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, >_PLANE_GAMC_1_B) >> +#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, >_PLANE_GAMC_2_B) >> +#define PLANE_GAMC(pipe, plane, i) \ >> + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), >_PLANE_GAMC_2(pipe)) >> + >> +#define _PLANE_GAMC16_1_A 0x70210 >> +#define _PLANE_GAMC16_1_B 0x71210 >> +#define _PLANE_GAMC16_2_A 0x70310 >> +#define _PLANE_GAMC16_2_B 0x71310 >> +#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \ >> + _PLANE_GAMC16_1_B) >> +#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \ >> + _PLANE_GAMC16_2_B) >> +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ >> + _PLANE_GAMC16_1(pipe), >_PLANE_GAMC16_2(pipe)) >> + >> /* pipe CSC & degamma/gamma LUTs on CHV */ >> #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) >> #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) >> diff --git a/drivers/gpu/drm/i915/intel_color.c >> b/drivers/gpu/drm/i915/intel_color.c >> index fb8402f..2b5c0cd 100644 >> --- a/drivers/gpu/drm/i915/intel_color.c >> +++ b/drivers/gpu/drm/i915/intel_color.c >> @@ -492,6 +492,59 @@ static void broadwell_load_luts(struct drm_crtc_state >*state) >> I915_WRITE(PREC_PAL_INDEX(pipe), 0); } >> >> +static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, >> + u32 offset) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); >> + enum pipe pipe = to_intel_plane(state->plane)->pipe; >> + enum plane_id plane = to_intel_plane(state->plane)->id; >> + uint32_t i, lut_size = >> + INTEL_INFO(dev_priv)- >>plane_color.plane_gamma_lut_size; >> + >> + if (state->gamma_lut) { >> + struct drm_color_lut_ext *lut = >> + (struct drm_color_lut_ext *) state->gamma_lut->data; >> + >> + for (i = 0; i < lut_size; i++) { >> + uint32_t word = >> + (drm_color_lut_extract(lut[i].red, 10) << 20) | >> + (drm_color_lut_extract(lut[i].green, 10) << 10) | >> + drm_color_lut_extract(lut[i].blue, 10); > > >Shouldn't you be using drm_color_lut_extract_ext ? For now, drm_color_lut_extract was enough. But will use the newly defined drm_color_lut_extract_ext to be future proof. Thanks for pointing this out. Regards, Uma Shankar > >> + >> + I915_WRITE(PLANE_GAMC(pipe, plane, i), word); >> + } >> + >> + /* Program the max register to clamp values > 1.0. */ >> + i = lut_size - 1; >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), >> + drm_color_lut_extract(lut[i].red, 16)); >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), >> + drm_color_lut_extract(lut[i].green, 16)); >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), >> + drm_color_lut_extract(lut[i].blue, 16)); >> + } else { >> + for (i = 0; i < lut_size; i++) { >> + uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); >> + >> + I915_WRITE(PLANE_GAMC(pipe, plane, i), >> + (v << 20) | (v << 10) | v); >> + } >> + >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1); >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1); >> + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1); >> + } >> +} >> + >> +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ static >> +void broadwell_load_plane_luts(const struct drm_plane_state *state) { >> + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); >> + >> + bdw_load_plane_gamma_lut(state, >> + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); >> +} >> + >> static void glk_load_degamma_lut(struct drm_crtc_state *state) { >> struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); @@ >> -648,6 +701,11 @@ void intel_plane_color_init(struct drm_plane *plane) >> >> drm_plane_color_create_prop(plane->dev, plane); >> >> + if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || >> + IS_BROXTON(dev_priv)) { >> + dev_priv->display.load_plane_luts = broadwell_load_plane_luts; >> + } >> + >> /* Enable color management support when we have degamma & gamma >LUTs. */ >> if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 && >> INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) >> diff --git a/drivers/gpu/drm/i915/intel_display.c >> b/drivers/gpu/drm/i915/intel_display.c >> index 690e1e8..2d15ac2 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -13803,6 +13803,10 @@ bool skl_plane_has_planar(struct >drm_i915_private *dev_priv, >> DRM_COLOR_YCBCR_BT709, >> >DRM_COLOR_YCBCR_LIMITED_RANGE); >> >> + /* Add Plane Color properties */ >> + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) >> + intel_plane_color_init(&primary->base); >> + >> drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); >> >> return primary; >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c >> b/drivers/gpu/drm/i915/intel_sprite.c >> index f7026e8..0eeb1d3 100644 >> --- a/drivers/gpu/drm/i915/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/intel_sprite.c >> @@ -1650,6 +1650,10 @@ struct intel_plane * >> DRM_COLOR_YCBCR_BT709, >> >DRM_COLOR_YCBCR_LIMITED_RANGE); >> >> + /* Add Plane Color properties */ >> + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) >> + intel_plane_color_init(&intel_plane->base); >> + >> drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); >> >> return intel_plane; >> -- >> 1.9.1 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > >-- >Cheers, >Alex G
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e931b48..40de78c 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -54,7 +54,10 @@ .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } #define BDW_COLORS \ - .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } + .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \ + .plane_color = { .plane_degamma_lut_size = 0, \ + .plane_gamma_lut_size = 16 } + #define CHV_COLORS \ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } #define GLK_COLORS \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0c9f03d..2db6a84 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -172,6 +172,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) +/* Plane Gamma Registers */ +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) +#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) + #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ if (__builtin_constant_p(mask)) \ @@ -9713,6 +9717,27 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) +/* Plane Gamma in Gen9+ */ +#define _PLANE_GAMC_1_A 0x701d0 +#define _PLANE_GAMC_1_B 0x711d0 +#define _PLANE_GAMC_2_A 0x702d0 +#define _PLANE_GAMC_2_B 0x712d0 +#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B) +#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B) +#define PLANE_GAMC(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe)) + +#define _PLANE_GAMC16_1_A 0x70210 +#define _PLANE_GAMC16_1_B 0x71210 +#define _PLANE_GAMC16_2_A 0x70310 +#define _PLANE_GAMC16_2_B 0x71310 +#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \ + _PLANE_GAMC16_1_B) +#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \ + _PLANE_GAMC16_2_B) +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ + _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index fb8402f..2b5c0cd 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -492,6 +492,59 @@ static void broadwell_load_luts(struct drm_crtc_state *state) I915_WRITE(PREC_PAL_INDEX(pipe), 0); } +static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + uint32_t i, lut_size = + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size; + + if (state->gamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *) state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + uint32_t word = + (drm_color_lut_extract(lut[i].red, 10) << 20) | + (drm_color_lut_extract(lut[i].green, 10) << 10) | + drm_color_lut_extract(lut[i].blue, 10); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), word); + } + + /* Program the max register to clamp values > 1.0. */ + i = lut_size - 1; + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), + drm_color_lut_extract(lut[i].red, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), + drm_color_lut_extract(lut[i].green, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), + drm_color_lut_extract(lut[i].blue, 16)); + } else { + for (i = 0; i < lut_size; i++) { + uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), + (v << 20) | (v << 10) | v); + } + + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1); + } +} + +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ +static void broadwell_load_plane_luts(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + + bdw_load_plane_gamma_lut(state, + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); +} + static void glk_load_degamma_lut(struct drm_crtc_state *state) { struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); @@ -648,6 +701,11 @@ void intel_plane_color_init(struct drm_plane *plane) drm_plane_color_create_prop(plane->dev, plane); + if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || + IS_BROXTON(dev_priv)) { + dev_priv->display.load_plane_luts = broadwell_load_plane_luts; + } + /* Enable color management support when we have degamma & gamma LUTs. */ if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 && INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..2d15ac2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13803,6 +13803,10 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv, DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); + /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&primary->base); + drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); return primary; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f7026e8..0eeb1d3 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1650,6 +1650,10 @@ struct intel_plane * DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); + /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&intel_plane->base); + drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); return intel_plane;
Implement Plane Gamma feature for BDW and Gen9 platforms. v2: Used newly added drm_color_lut_ext structure for enhanced precision for Gamma LUT entries. v3: Rebase Signed-off-by: Uma Shankar <uma.shankar@intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 5 +++- drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++ drivers/gpu/drm/i915/intel_color.c | 58 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 4 +++ drivers/gpu/drm/i915/intel_sprite.c | 4 +++ 5 files changed, 95 insertions(+), 1 deletion(-)