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[0/5] H3/M3-W cpuidle support

Message ID 1534511968-19634-1-git-send-email-uli+renesas@fpond.eu (mailing list archive)
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Series H3/M3-W cpuidle support | expand

Message

Ulrich Hecht Aug. 17, 2018, 1:19 p.m. UTC 
Hi!

This series adds CPU idle support for H3 and M3-W. It's a straight
up-port from the BSP.

The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
SoC?

CU
Uli


Dien Pham (2):
  arm64: dts: r8a7795: Add cpuidle support for CA53 cores
  arm64: dts: r8a7796: Add cpuidle support for CA53 cores

Khiem Nguyen (2):
  arm64: dts: r8a7795: Add cpuidle support for CA57 cores
  arm64: dts: r8a7796: Add cpuidle support for CA57 cores

Takeshi Kihara (1):
  arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

 arch/arm64/boot/dts/renesas/r8a7795.dtsi       | 32 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796.dtsi       | 30 ++++++++++++++++++++++++
 3 files changed, 84 insertions(+)

Comments

Geert Uytterhoeven Aug. 23, 2018, 8:22 a.m. UTC | #1 
Hi Uli,

On Fri, Aug 17, 2018 at 3:19 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This series adds CPU idle support for H3 and M3-W. It's a straight
> up-port from the BSP.

Thanks for your series!

> The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
> dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
> SoC?

Alternatively, is this something that can be handled in the kernel using
soc_device_match()?

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven Aug. 23, 2018, 8:30 a.m. UTC | #2 
Hi Uli,

(with Khiem's address fixed (hopefully))

On Thu, Aug 23, 2018 at 10:22 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Fri, Aug 17, 2018 at 3:19 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> > This series adds CPU idle support for H3 and M3-W. It's a straight
> > up-port from the BSP.
>
> Thanks for your series!
>
> > The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
> > dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
> > SoC?
>
> Alternatively, is this something that can be handled in the kernel using
> soc_device_match()?

Given many Salvator-X boards (incl. mine) also have M3-W ES1.0, and PSCI is
involved, I have to ask: is this a hardware (M3-W ES1.0) or firmware (PSCI)
issue?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds