arm64: dts: rockchip: perfection vop property define for px30

Commit Message

黄家钗 Aug. 29, 2018, 3:17 a.m. UTC

Add display ports for display-subsystem and add reset property
for vop node, if missing this two define, drm driver can't
probe sucess.

Signed-off-by: Sandy Huang <[e-mail]>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Heiko Stübner Aug. 29, 2018, 12:57 p.m. UTC | #1

Am Mittwoch, 29. August 2018, 05:17:13 CEST schrieb Sandy Huang:
> Add display ports for display-subsystem and add reset property
> for vop node, if missing this two define, drm driver can't
> probe sucess.
> 
> Signed-off-by: Sandy Huang <[e-mail]>

with a bit of cleanup applied for 4.20

Thanks
Heiko

Patch

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index dc3b22c..b2f1716 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -157,6 +157,7 @@ 
 
 	display_subsystem: display-subsystem {
 		compatible = "rockchip,display-subsystem";
+		ports = <&vopb_out>, <&vopl_out>;
 		status = "disabled";
 	};
 
@@ -795,10 +796,16 @@ 
 		clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
 			 <&cru HCLK_VOPB>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
+		reset-names = "axi", "ahb", "dclk";
 		iommus = <&vopb_mmu>;
 		power-domains = <&power PX30_PD_VO>;
 		rockchip,grf = <&grf>;
 		status = "disabled";
+		vopb_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 
 	vopb_mmu: iommu@ff460f00 {
@@ -820,10 +827,16 @@ 
 		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
 			 <&cru HCLK_VOPL>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
+		reset-names = "axi", "ahb", "dclk";
 		iommus = <&vopl_mmu>;
 		power-domains = <&power PX30_PD_VO>;
 		rockchip,grf = <&grf>;
 		status = "disabled";
+		vopl_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 
 	vopl_mmu: iommu@ff470f00 {