| Message ID | 1535695223-4648-1-git-send-email-jyoti.r.yadav@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. | expand |
On Fri, Aug 31, 2018 at 08:00:41AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/intel_csr.c Fix DMC FW Loading issue on ICL. (rev6) > URL : https://patchwork.freedesktop.org/series/48803/ > State : success Pushed to -dinq thanks for the patch and review. I also added the update request to BSpec about units for the offset field. > > == Summary == > > = CI Bug Log - changes from CI_DRM_4745_full -> Patchwork_10057_full = > > == Summary - WARNING == > > Minor unknown changes coming with Patchwork_10057_full need to be verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_10057_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > == Possible new issues == > > Here are the unknown changes that may have been introduced in Patchwork_10057_full: > > === IGT changes === > > ==== Warnings ==== > > igt@kms_concurrent@pipe-b: > shard-snb: SKIP -> PASS +1 > > igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-xtiled: > shard-snb: PASS -> SKIP +1 > > > == Known issues == > > Here are the changes found in Patchwork_10057_full that come from known issues: > > === IGT changes === > > ==== Issues hit ==== > > igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: > shard-hsw: PASS -> FAIL (fdo#105767) > > igt@kms_cursor_legacy@cursor-vs-flip-toggle: > shard-hsw: PASS -> FAIL (fdo#103355) > > > ==== Possible fixes ==== > > igt@drv_suspend@shrink: > shard-hsw: INCOMPLETE (fdo#106886, fdo#103540) -> PASS > shard-apl: INCOMPLETE (fdo#106886, fdo#103927) -> PASS > shard-glk: FAIL (fdo#106886) -> PASS > > igt@gem_ppgtt@blt-vs-render-ctxn: > shard-kbl: INCOMPLETE (fdo#103665, fdo#106023) -> PASS > > igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: > shard-glk: FAIL (fdo#105363) -> PASS +1 > > > fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 > fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 > fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 > fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 > fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 > fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 > fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 > fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886 > > > == Participating hosts (5 -> 5) == > > No changes in participating hosts > > > == Build changes == > > * Linux: CI_DRM_4745 -> Patchwork_10057 > > CI_DRM_4745: 4ddf5e7833fae7268e674ddea403a24b36c8337d @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_4612: e39e09910fc8e369e24f6a0cabaeb9356dbfae08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_10057: 225ce5d7d0c64e3c963e105a4e8d05d4533539fe @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10057/shards.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 1ec4f09..14cf4c3 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -55,7 +55,9 @@ #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) -#define CSR_MAX_FW_SIZE 0x2FFF +#define BXT_CSR_MAX_FW_SIZE 0x3000 +#define GLK_CSR_MAX_FW_SIZE 0x4000 +#define ICL_CSR_MAX_FW_SIZE 0x6000 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF struct intel_css_header { @@ -279,6 +281,7 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, struct intel_csr *csr = &dev_priv->csr; const struct stepping_info *si = intel_get_stepping_info(dev_priv); uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; + uint32_t max_fw_size = 0; uint32_t i; uint32_t *dmc_payload; uint32_t required_version; @@ -359,6 +362,8 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, si->stepping); return NULL; } + /* Convert dmc_offset into number of bytes. By default it is in dwords*/ + dmc_offset *= 4; readcount += dmc_offset; /* Extract dmc_header information. */ @@ -391,8 +396,16 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ nbytes = dmc_header->fw_size * 4; - if (nbytes > CSR_MAX_FW_SIZE) { - DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes); + if (INTEL_GEN(dev_priv) >= 11) + max_fw_size = ICL_CSR_MAX_FW_SIZE; + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + max_fw_size = GLK_CSR_MAX_FW_SIZE; + else if (IS_GEN9(dev_priv)) + max_fw_size = BXT_CSR_MAX_FW_SIZE; + else + MISSING_CASE(INTEL_REVID(dev_priv)); + if (nbytes > max_fw_size) { + DRM_ERROR("DMC FW too big (%u bytes)\n", nbytes); return NULL; } csr->dmc_fw_size = dmc_header->fw_size;